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a sharc and the sharc logo are registered trademarks of ana log devices, inc. commercial grade sharc dsp microcomputer adsp-21061 / adsp-21061l rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all rights reserved. technical support www.analog.com summary high performance signal processor for communications, graphics, and imaging applications super harvard architecture four independent buses for dual data fetch, instruction fetch, and nonintrusive i/o 32-bit ieee floating-point computation unitsmultiplier, alu, and shifter dual-ported on-chip sram and integrated i/o peripheralsa complete system-on-a-chip integrated multiprocessing features key featuresprocessor core 50 mips, 20 ns instruction ra te, single-cycle instruction execution 120 mflops peak, 80 mflops sustained performance dual data address generators with modulo and bit-reverse addressing efficient program sequencing with zero-overhead looping: single-cycle loop setup ieee jtag standard 1149.1 test access port and on-chip emulation 32-bit single-precision and 40-bit extended-precision ieee floating-point data formats or 32-bit fixed-point data format 240-lead mqfp package, thermally enhanced mqfp, 225-ball plastic ball grid array (pbga) lead (pb) free packages. for more information, see ordering guide on page 52. figure 1. function al block diagram mult barrel serial ports (2) 4 6 6 iop registers (memory mapped) control, status and data buffers i/o processor timer instruction cache addr data data addr addr data addr two independent dual-ported blocks processor port i/o port dual-ported sram jtag test and emulation 7 host port addr bus mux ioa 17 iod 48 multiprocessor interface external port data bus mux 48 32 24 dm address bus pm data bus dm data bus bus connect (px) dag1 32 48 40/32 core processor program sequencer b lock 0 block 1 8 4 32 dag2 8 4 24 32 48-bit pm address bus data controller dma data register file 16 40-bit s alu shifter
rev. d | page 2 of 52 | may 2013 adsp-21061 / adsp-21061l table of contents summary ............................................................... 1 key featuresprocessor core ................................. 1 general description ................................................. 3 sharc family core architecture ............................ 3 memory and i/o interface features ........................... 4 porting code from the adsp-21060 or adsp-21062 ..................................................... 7 development tools ............................................... 7 additional information .......................................... 8 related signal chains ............................................ 8 pin function descriptions ......................................... 9 target board connector for ez-ice probe ............... 12 adsp-21061 specifications . ..................................... 14 operating conditions (5 v) ................................... 14 electrical characteristics (5 v) ............................... 14 internal power dissipation (5 v) ............................ 15 external power dissipation (5 v) ............................ 16 adsp-21061l specifications .. ................................... 17 operating conditions (3.3 v) ................................. 17 electrical characteristics (3.3 v) ............................. 17 internal power dissipation (3.3 v) .......................... 18 external power dissipation (3.3 v) .......................... 19 absolute maximum ratings ................................... 20 esd caution ...................................................... 20 package marking information ................................ 20 timing specifications ........................................... 20 test conditions .................................................. 43 environmental conditions .................................... 46 225-ball pbga pin configurations ............................. 47 240-lead mqfp pin configurations .. ......................... 49 outline dimensions ................................................ 50 surface-mount design .......................................... 52 ordering guide ..................................................... 52 revision history 5/13rev c to rev d updated development tools .......................................7 added related signal chains .......................................8 removed the adsp-21061las-1 76, adsp-21061lks-160, and adsp-21061lks-176 models from ordering guide ........ 52 general note this data sheet represents production released specifications for the adsp-21061 (5 v) and adsp- 21061l (3.3 v) processors for 33 mhz, 40 mhz, 44 mhz, and 50 mhz speed grades. the product nameadsp-21061 is used throughout this data sheet to represent all devices, except where expressly noted.
adsp-21061 / adsp-21061l rev. d | page 3 of 52 | may 2013 general description the adsp-21061 sharcsuper harvard architecture com- puteris a signal processing microcomputer that offers new capabilities and levels of performance. the adsp-21061 sharc is a 32-bit processor op timized for high performance dsp applications. the adsp-21061 builds on the adsp-21000 dsp core to form a complete system-on-a-chip, adding a dual- ported on-chip sram and integr ated i/o peripherals supported by a dedicated i/o bus. fabricated in a high speed, low power cmos process, the adsp-21061 has a 20 ns instructio n cycle time and operates at 50 mips. with its on-chip instru ction cache, the processor can execute every instruction in a single cycle. table 1 shows perfor- mance benchmarks for the adsp-21061/adsp-21061l. the adsp-21061 sharc represents a new standard of integra- tion for signal computers, combining a high performance floating-point dsp core with integrated, on-chip system fea- tures including 1m bit sram memory, a host processor interface, a dma controller, seri al ports, and parallel bus con- nectivity for glueless dsp multiprocessing. the adsp-21061 continues sharc s industry-leading stan- dards of integration for dsps, combining a high performance 32-bit dsp core with integrated, on-chip system features. the block diagram on page 1 , illustrates the following architec- tural features: ? computation units (alu, multiplier, and shifter) with a shared data register file ? data address generators (dag1, dag2) ? program sequencer with instruction cache ? pm and dm buses capable of supporting four 32-bit data transfers between me mory and the core at every core pro- cessor cycle ?interval timer ?on-chip sram ? external port for interfacing to off-chip memory and peripherals ? host port and multiprocessor interface ? dma controller ?serial ports ? jtag test access port sharc family core architecture the adsp-21061 includes the follo wing architectural features of the adsp-21000 family core . the adsp-21061 processors are code- and function-compa tible with the adsp-21020, adsp-21060, and adsp-21062 sharc processors. independent, parallel computation units the arithmetic/logic unit (alu), multiplier, and shifter all per- form single-cycle instructions. the three units are arranged in parallel, maximizing computatio nal throughput. single multi- function instructions execute pa rallel alu and multiplier oper- ations. these computation units support ieee 32-bit single- precision floating-point, extended-precision 40-bit floating- point, and 32-bit fixed-point data formats. data register file a general-purpose data register file is used for transferring data between the computation units and the data buses, and for stor- ing intermediate results. this 10-port, 32-register (16 primary, 16 secondary) register file, combined with the adsp-21000 harvard architecture, allows unconstrained data flow between computation units and internal memory. table 1. benchmarks (at 50 mhz) benchmark algorithm speed cycles 1024 point complex fft (radix 4, with reversal) .37 ms 18,221 fir filter (per tap) 20 ns 1 iir filter (per biquad) 80 ns 4 divide (y/x) 120 ns 6 inverse square root 180 ns 9 dma transfer rate 300m bps figure 2. adsp-21061/adsp-21061l system sample configuration 3 4 reset jtag 7 ad s p-21061 bms 1 clock cs boot eprom ( optional ) memory- mapped devices ( optional ) oe data dma device ( optional ) data addr data host processor interface ( optional ) cs rd page adrclk ack br 1C6 dmar 1C2 clkin irq 2C0 tclk0 rpba eboot lboot flag 3 C0 timexp dr0 dt0 rsf0 tfs0 rclk0 tclk1 dr1 dt1 rsf1 tfs1 rclk1 id 2C0 serial device ( optional ) serial device ( optional ) cpa redy hbg hbr dmag 1C2 sbts ms 3 C0 wr data 47C0 data addr cs ack we addr 3 1C0 d a t a c o n t r o l a d d r e s s addr to gnd sw
rev. d | page 4 of 52 | may 2013 adsp-21061 / adsp-21061l single-cycle fetch of instruction and two operands the adsp-21061 features an enhanc ed harvard architecture in which the data memory (dm) bu s transfers data and the pro- gram memory (pm) bus transfer s both instructions and data ( figure 1 on page 1 ). with its separate program and data mem- ory buses and on-chip instruct ion cache, the processor can simultaneously fetch two operands and an instruction (from the cache), all in a single cycle. instruction cache the adsp-21061 includes an on-c hip instructio n cache that enables three-bus operation for fe tching an instruction and two data values. the cache is select iveonly the instructions whose fetches conflict with pm bus data accesses are cached. this allows full-speed execution of co re, looped operations such as digital filter multiply-accumulat es and fft butterfly processing. data address generators with hardware circular buffers the adsp-21061s two data addre ss generators (dags) imple- ment circular data buffers in hardware. circular buffers allow efficient programming of delay li nes and other data structures required in digital signal proce ssing, and are commonly used in digital filters and fourier tran sforms. the two dags of the adsp-21061 contain sufficient regist ers to allow the creation of up to 32 circular buffers (16 pr imary register sets, 16 secondary). the dags automatically handle address pointer wraparound, reducing overhead, increasing performance and simplifying implementation. circular buffers can start and end at any mem- ory location. flexible instruction set the 48-bit instruction word acco mmodates a variety of parallel operations, for concise programming. for example, the adsp-21061 can conditionally ex ecute a multiply, an add, a subtract, and a branch, all in a single instruction. memory and i/o interface features the adsp-21061 processors add the following architectural features to the sharc family core. dual-ported on-chip memory the adsp-21061 contains one mega bit of on-chip sram, orga- nized as two blocks of 0.5m bits each. each bank has eight 16-bit columns with 4k 16-bi t words per column. each memory block is dual-ported for single-cycle, independent accesses by the core processor and i/o processor or dma controller. the dual- ported memory and separate on-chip buses allow two data transfers from the core and one from i/o, all in a single cycle (see figure 4 for the adsp-21061 memory map). on the adsp-21061, the memory ca n be configured as a maxi- mum of 32k words of 32-bit data , 64k words for 16-bit data, 16k words of 48-bit instructions (and 40-bit data) or combinations of different word sizes up to 1 megabit. all the memory can be accessed as 16-bit, 32-bit, or 48-bit. a 16-bit floating-point storage format is supported, which effec- tively doubles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit float- ing-point formats is done in a single instruction. while each memory block can st ore combinations of code and data, accesses are most efficien t when one block stores data, using the dm bus for transfers, and the other block stores instructions and data, using the pm bus for transfers. using the dm bus and pm bus in this way, with one dedicated to each memory block, assures single-c ycle execution with two data transfers. in this ca se, the instruction must be available in the cache. single-cycle execution is also maintained when one of the data operands is transferred to or from off-chip, via the adsp-21061s external port. off-chip memory and peripherals interface the adsp-21061s external port pr ovides the processors inter- face to off-chip memory and pe ripherals. the 4-gigaword off- chip address space is includ ed in the adsp-21061s unified address space. the separate on-chip busesfor program mem- ory, data memory, and i/oare mu ltiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 48-bit (or 32-bit) da ta bus. the on-chip super har- vard architecture provides th ree-bus performance, while the off-chip unified address space gives flexibility to the designer. addressing of external memory devices is facilitated by on-chip decoding of high order address lines to generate memory bank select signals. separa te control lines are also generated for sim- plified addressing of page -mode dram. the adsp-21061 provides programmable memory wait states and external mem- ory acknowledge controls to a llow interfacing to dram and peripherals with variable ac cess, hold, and disable time requirements. host processor interface the adsp-21061s host interface allows easy connection to standard microprocessor buses, both 16-bit and 32-bit, with lit- tle additional hardware required. asynchronous transfers at speeds up to the full clock rate of the processor are supported. the host interface is accesse d through the adsp-21061s exter- nal port and is memory-mapped into the unified address space. two channels of dma are available for the host interface; code and data transfers are accomp lished with low software overhead. the host processor requests the adsp-21061s external bus with the host bus request (hbr ), host bus grant (hbg ), and ready (redy) signals. the host can directly read and write the internal memory of the adsp -21061, and can access the dma channel setup and mailbox register s. vector interrupt support is provided for efficient exec ution of host commands. dma controller the adsp-21061s on-chip dma controller allows zero- overhead data transfers withou t processor intervention. the dma controller operates indepe ndently and invisibly to the processor core, allowing dma operations to occur while the core is simultaneously executing its program instructions.
adsp-21061 / adsp-21061l rev. d | page 5 of 52 | may 2013 dma transfers can occur between the adsp-21061s internal memory and either external memory, external peripherals, or a host processor. dma transfer s can also occur between the adsp-21061s internal memory and its serial ports. dma transfers between external memory and external periph- eral devices are another option. external bus packing to 16-, 32-, or 48-bit words is perf ormed during dma transfers. figure 3. shared memory multiprocessing system addr 3 1C0 cpa bms c o n t r o l ad s p-21061 #1 5 control ad s p-21061 #2 addr 3 1C0 control ad s p-21061 # 3 5 id2C0 reset rpba clkin id2C0 reset rpba id2C0 reset rpba clkin ad s p-21061 #6 ad s p-21061 #5 ad s p-21061 #4 clock re s et addr data ho s tproce ss or interface (optional) ack global memory and peripheral (optional) oe addr data cs addr data boot eprom (optional) rdx ms3C0 sbts cs ack addr 3 1C0 clkin 3 001 page 3 010 3 011 br1 br2C6 redy hbg hbr cs we wrx 5 c o n t r o l a d d r e s s d a t a c o n t r o l a d d r e s s d a t a data47C0 br1C2, br4C6 br3 data47C0 br1, br3C6 br2 data47C0 bu s priority cpa
rev. d | page 6 of 52 | may 2013 adsp-21061 / adsp-21061l six channels of dma are avai lable on the adsp-21061four via the serial ports, and two via th e processors external port (for either host processor, othe r adsp-21061s, memory or i/o transfers). programs can be downloaded to the adsp-21061 using dma transfers. asynchrono us off-chip peripherals can control two dma channels us ing dma request/grant lines (dmar 1C2 , dmag 1C2 ). other dma features include interrupt generation upon completion of dma transfers and dma chaining for automatic linked dma transfers. serial ports the adsp-21061 features two synchronous se rial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. the serial ports can operate at the full clock rate of the processor, providing each with a maxi- mum data rate of up to 50 mb ps. independent transmit and receive functions provide greater flexibility for serial communi- cations. serial port data can be automatically transferred to and from on-chip memory via dma. each of the serial ports offers tdm multichannel mode. the serial ports can operate with little-endian or big-endian transmission formats, with word lengths sele ctable from 3 bits to 32 bits. they offer selectable synchronization and transmit modes as well as optional -law or a-law companding. serial port clocks and frame syncs can be internally or externally gen- erated. the serial ports also include keyword and key mask features to enhance interprocessor communication. multiprocessing the adsp-21061 offers powerful fe atures tailored to multipro- cessor dsp systems. the un ified address space (see figure 4 ) allows direct interprocessor accesses of each adsp-21061s internal memory. distributed bus arbitration logic is included on-chip for simple, glueless conn ection of systems containing up to six adsp-21061s and a host processor. master processor changeover incurs only one cycle of overhead. bus arbitration is selectable as either fixed or ro tating priority. bus lock allows indivisible read-modify-write se quences for semaphores. a vec- tor interrupt is provided for interprocessor commands. maxi- mum throughput for interprocesso r data transfer is 500 mbps over the external port. broadc ast writes allo w simultaneous transmission of data to all adsp-21061s and can be used to implement reflective semaphores. figure 4. memory map 0x0004 0000 0x0010 0000 0x000 8 0000 0x001 8 0000 0x0012 0000 0x002 8 0000 0x00 38 0000 0x0000 0000 0x0002 0000 0x0040 0000 bank 1 ms0 bank 2 ms1 bank 3 ms2 ms3 iop regi s ter s s hort word addre ss ing (16-bit data word s ) normal word addre ss ing ( 3 2-bit data word s 4 8 -bit in s truction word s ) addre ss bank 0 s dram (optional) 0x0fff ffff nonbanked note: bank s ize s are s elected by m s ize bit s of the s y s con regi s ter 0x00 3 0 0000 internal memory s pace multiproce ss or memory s pace addre ss internal memory s pace with id = 001 0 x 00 3 f ffff external memory s pace internal memory s pace with id = 010 internal memory s pace with id = 011 internal memory s pace with id = 100 internal memory s pace with id = 101 internal memory s pace with id = 110 broadca s twrite to all ad s p-21061s
adsp-21061 / adsp-21061l rev. d | page 7 of 52 | may 2013 program booting the internal memory of the ad sp-21061 can be booted at sys- tem power-up from either an 8-bit eprom, or a host processor. selection of the boot source is controlled by the bms (boot memory select), eboot (eprom boot), and lboot (host boot) pins. 32-bit and 16-bit host processors can be used for booting. porting code from the adsp-21060 or adsp-21062 the adsp-21061 is pin compat ible with the adsp-21060/ adsp-21061/adsp-21062 proce ssors. the adsp-21061 pins that correspond to the link port pins of the adsp-21060/ adsp-21062 are no-connects. the adsp-21061 is object co de compatible with the adsp-21060/adsp-21062 processors except for the following functional elements: ? the adsp-21061 memory is or ganized into two blocks with eight columns that are 4k deep per block. the adsp-21060/adsp-21062 memory has 16 columns per block. ? link port functions are not available. ? handshake external port dma pins dmar2 and dmag2 are assigned to external port dma channel 6 instead of channel 8. ? 2-d dma capability of the sport is not available. ? the modify registers in sport dma are not programmable. on the adsp-21061, block 0 starts at the beginnin g of internal memory, normal word address 0x0002 0000. block 1 starts at the end of block 0, with contig uous addresses. the remaining addresses in internal memory are divided into blocks that alias into block 1. this allows any code or data stored in block 1 on the adsp-21062 to retain th e same addresses on the adsp- 21061these addresses will al ias into the actual block 1 of each processor. if you develop your applicatio n using the adsp-21062, but will migrate to the adsp-21061, use on ly the first eight columns of each memory bank. limit your appl ication to 8k of instructions or up to 16k of data in each bank of the adsp-21062, or any combination of instructions or data that does not exceed the memory bank. development tools analog devices supports its proce ssors with a complete line of software and hardware development tools, including integrated development environments (which include crosscore ? embed- ded studio and/or visualdsp++ ? ), evaluation products, emulators, and a wide vari ety of software add-ins. integrated development environments (ides) for c/c++ software writing and editing, code generation, and debug support, analog devices offers two ides. the newest ide, crosscore embe dded studio, is based on the eclipse tm framework. supporting most analog devices proces- sor families, it is the ide of choice for future processors, including multicore devices. crosscore embedded studio seamlessly integrates available so ftware add-ins to support real time operating systems, file systems, tcp/ip stacks, usb stacks, algorithmic software modules, and evaluation hardware board support packages. for more information visit www.analog.com/cces . the other analog devices ide, visualdsp++, supports proces- sor families introduced prior to the release of crosscore embedded studio. this ide incl udes the analog devices vdk real time operating system and an open source tcp/ip stack. for more information visit www.analog.com/visualdsp . note that visualdsp++ will not suppo rt future analog devices processors. ez-kit lite evaluation board for processor evaluation, analog devices provides wide range of ez-kit lite ? evaluation boards. incl uding the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. also available are various ez-extenders ? , which are daughter cards delivering additional specialized functionality, including audio and video processing. for more information visit www.analog.com and search on ezkit or ezextender. ez-kit lite evaluation kits for a cost-effective way to lear n more about developing with analog devices processors, analog devices offer a range of ez- kit lite evaluation kits. each evaluation kit includes an ez-kit lite evaluation board, directions for downloading an evaluation version of the available ide(s), a usb cable, and a power supply. the usb controller on the ez-kit lite board connects to the usb port of the users pc, enab ling the chosen ide evaluation suite to emulate the on-board pr ocessor in-circuit. this permits the customer to download, execut e, and debug programs for the ez-kit lite system. it also su pports in-circuit programming of the on-board flash device to store user-specific boot code, enabling standalone operation. with the full version of cross- core embedded studio or visualdsp++ installed (sold separately), engineers can deve lop software for supported ez- kits or any custom system util izing supported analog devices processors. software add-ins for crosscore embedded studio analog devices offers software add-ins which seamlessly inte- grate with crosscore embedded stud io to extend its capabilities and reduce development time. add-ins include board support packages for evaluation hardwa re, various middleware pack- ages, and algorithmic modules. documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through th e crosscore embedded studio ide once the add-in is installed.
rev. d | page 8 of 52 | may 2013 adsp-21061 / adsp-21061l board support packages for evaluation hardware software support for the ez-kit lite evaluation boards and ez- extender daughter cards is prov ided by software add-ins called board support packages (bsps). the bsps contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. a downlo ad link for a specific bsp is located on the web page for the associated ez-kit or ez- extender product. the link is found in the product download area of the product web page. middleware packages analog devices separately offers middleware add-ins such as real time operating systems, file systems, usb stacks, and tcp/ip stacks. for more information see the following web pages: ? www.analog.com/ucos3 ? www.analog.com/ucfs ? www.analog.com/ucusbd ? www.analog.com/lwip algorithmic modules to speed development, analog de vices offers add-ins that per- form popular audio and video processing algorithms. these are available for use with both cr osscore embedded studio and visualdsp++. for more information visit www.analog.com and search on blackfin software modules or sharc software modules. designing an emulator-compatible dsp board (target) for embedded system test and de bug, analog devices provides a family of emulators. on each jtag dsp, analog devices sup- plies an ieee 1149.1 jtag test access port (tap). in-circuit emulation is facilitated by use of this jtag interface. the emu- lator accesses the processors internal features via the processors tap, allowing the de veloper to load code, set break- points, and view variables, memory, and registers. the processor must be halted to se nd data and commands, but once an operation is completed by the emulator, the dsp system is set to run at full speed with no im pact on system timing. the emu- lators require the target board to include a header that supports connection of the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices website ( www.analog.com )use site search on ee-68. this document is updated regularly to keep pace with improvements to emulator support. additional information this data sheet provides a ge neral overview of the adsp-21061 architecture and functionality. for detailed information on the adsp-21000 family core architectu re and instruction set, refer to the adsp- 2106x sharc users manual . related signal chains a signal chain is a series of signal co nditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the signal chain entry in the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal processing comp onents that are designed to work together well. a tool fo r viewing relationships between specific applications and related components is available on the www.analog.com website. the circuits from the lab tm site ( www.analog.com/signal chains ) provides: ? graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques
adsp-21061 / adsp-21061l rev. d | page 9 of 52 | may 2013 pin function descriptions adsp-21061 pin definitions are list ed below. all pins are identi- cal on the adsp-21061 and adsp- 21061l. inputs identified as synchronous (s) must meet timing requirements with respect to clkin (or with respect to tck for tms, tdi). inputs identi- fied as asynchronous (a) can be asserted asynchronously to clkin (or to tck for trst ). unused inputs should be tied or pulled to vdd or gnd, except for addr31-0, data47-0, flag3-0, sw , and inputs that have internal pull-up or pu ll-down resistors (cpa , ack, dtx, drx, tclkx, rclkx, tms, and tdi)t hese pins can be left float- ing. these pins have a logic-leve l hold circuit that prevents the input from floating internally. table 2. pin descriptions pin type function addr 31C0 i/o/t external bus address. the adsp-21061 outputs addresses for external memory and peripherals on these pins. in a multiprocessor system the bus master outputs addresses for read/write of the internal memory or iop registers of other adsp-21061s. the adsp-21061 in puts addresses when a host processor or multipro- cessing bus master is reading or writin g its internal memory or iop registers. data 47C0 i/o/t external bus data. the adsp-21061 inputs and outputs data and instructions on these pins. 32-bit single- precision floating-point data and 32-bit fixed-point data is transferred over bits 47 to 16 of the bus. 40-bit extended-precision floating-poi nt data is transferred over bits 47 to 8 of the bus. 16-bit short word data is transferred over bits 31 to 16 of the bus. in prom boot mode, 8-bit data is transferre d over bits 23 to 16. pull- up resistors on unused data pins are not necessary. ms 3C0 o/t memory select lines. these lines are asserted (low) as chip sele cts for the corresponding banks of external memory. memory bank size must be defined in the adsp-21061s system control register (syscon). the ms 3C0 lines are decoded memory address lines that change at the same time as the other address lines. when no external memory access is occurring the ms 3C0 lines are inactive; they are active however when a conditional memory access instruction is executed, whether or not the condition is true. ms 0 can be used with the page signal to implement a bank of dram memory (bank 0). in a multiprocessing system the ms 3C0 lines are output by the bus master. rd i/o/t memory read strobe. this pin is asserted (low) when the adsp-21061 reads from external memory devices or from the internal memory of other adsp-21061s. external devices (including other adsp-21061s) must assert rd to read from the adsp-21061s internal memory. in a multiprocessing system rd is output by the bus master and is input by all other adsp-21061s. wr i/o/t memory write strobe. this pin is asserted (low) when the adsp-21061 writes to external memory devices or to the internal memory of other adsp-21061s. external devices must assert wr to write to the adsp-21061s internal memory. in a multiprocessing system wr is output by the bus master and is input by all other adsp-21061s. page o/t dram page boundary. the adsp-21061 asserts this pin to signal that an external dram page boundary has been crossed. dram page size must be defined in the adsp-21061s memory control register (wait). dram can only be implemented in external memory bank 0; the page signal can only be activated for bank 0 accesses. in a multiprocessing system page is output by the bus master. adrclk o/t clock output reference. in a multiprocessing system adrc lk is output by the bus master. sw i/o/t synchronous write select. this signal is used to interface the adsp-21061 to synchronous memory devices (including other adsp-21061s) . the adsp-21061 asserts sw (low) to provide an early indication of an impending write cycle, which can be aborted if wr is not later asserted (e.g., in a conditional write instruction). in a multiprocessing system, sw is output by the bus master and is input by all other adsp-21061s to determine if the multiprocessor memory access is a read or write. sw is asserted at the same time as the address output. a host pr ocessor using synchronous writes must assert this pin when writing to the adsp-21061(s). a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open-drai n, t = three-state (when sbts is asserted, or when the adsp-21061 is a bus slave)
rev. d | page 10 of 52 | may 2013 adsp-21061 / adsp-21061l ack i/o/s memory acknowledge. external devices can deassert ack (low) to add wait states to an external memory access. ack is used by i/o devices, memory controllers , or other peripherals to ho ld off completion of an external memory access. the adsp-21061 deasserts ack as an output to add wait states to a synchronous access of its internal memory. in a multiprocessing sy stem, a slave adsp-21061 de asserts the bus masters ack input to add wait state(s) to an access of its inte rnal memory. the bus master has a keeper latch on its ack pin that maintains the input at the level to which it was last driven. sbts i/s suspend bus three-state. external devices can assert sbts (low) to place the external bus address, data, selects, and strobes in a high impedance state for the following cycle. if the adsp-21061 attempts to access external memory while sbts is asserted, the processor halts and the memory access is not complete until sbts is deasserted. sbts should only be used to recover from ho st processor/adsp-21061 deadlock, or used with a dram controller. irq 2C0 i/a interrupt request lines. may be either edge-triggered or level-sensitive. flag 3C0 i/o/a flag pins. each is configured via control bits as either an in put or output. as an input, they can be tested as a condition. as an output, they can be used to signal ex ternal peripherals. timexp o timer expired. asserted for four cycles when the timer is enabled and tcount decrements to zero. hbr i/a host bus request. this pin must be asserted by a host proc essor to request control of the adsp-21061s external bus. when hbr is asserted in a multiprocessing system , the adsp-21061 that is bus master will relinquish the bus and assert hbg . to relinquish the bus, the adsp-21061 places the address, data, select, and strobe lines in a high impedance state. hbr has priority over all adsp-21061 bus requests br 6C1 in a multiprocessing system. hbg i/o host bus grant. acknowledges a bus request, indicating that the host processor may take control of the external bus. hbg is asserted (held low) by the adsp-21061 until hbr is released. in a multiprocessing system, hbg is output by the adsp-21061 bus master and is monitored by all others. cs i/a chip select. asserted by host processor to select the adsp-21061. redy o (o/d) host bus acknowledge. the adsp-21061 deasserts redy (low) to add wait states to an asynchronous access of its internal memory or iop registers by a host. this pin is an open-drain output (o/d) by default; it can be programmed in the adredy bit of the syscon register to be active drive (a/d). redy will only be output if the cs and hbr inputs are asserted. dmar 2C1 i/a dma request 1 (dma channel 7) and dma request 2 (dma channel 6). dmag 2C1 o/t dma grant 1 (dma channel 7) and dma grant 2 (dma channel 6). br 6C1 i/o/s multiprocessing bus requests. used by multiprocessing adsp-21061 processors to arbitrate for bus mastership. an adsp-21061 only drives its own br x line (corresponding to the value of its id2-0 inputs) and monitors all others. in a multiprocessor system with less than six adsp-21061s, the unused br x pins should be pulled high; the processors own br x line must not be pulled high or low because it is an output. id2C0 o (o/d) multiprocessing id. determines which multiprocessing bus request (br1 C br6 ) is used by adsp-21061. id = 001 corresponds to br1 , id = 010 corresponds to br2 , etc., id = 000 in single-processor systems. these lines are a system configuration selection which should be hardwi red or changed at reset only. rpba i/s rotating priority bus arbitration select. when rpba is high, rotating pr iority for multiprocessor bus arbitration is selected. when rpba is low, fixed priori ty is selected. this signal is a system configuration selection which must be set to the same value on ever y adsp-21061. if the value of rpba is changed during system operation, it must be changed in the same clkin cycle on every adsp-21061. cpa i/o (o/d) core priority access. asserting its cpa pin allows the core processor of an adsp-21061 bus slave to interrupt background dma transfers and gain access to the external bus. cpa is an open-drain output that is connected to all adsp-21061s in the system. the cpa pin has an internal 5 k ? pull-up resistor. if core access priority is not required in a system, the cpa pin should be left unconnected. dtx o data transmit (serial ports 0, 1). each dt pin has a 50 k ? internal pull-up resistor. drx i data receive (serial ports 0, 1). each dr pin has a 50 k ? internal pull-up resistor. tclkx i/o transmit clock (serial ports 0, 1). each tclk pin has a 50 k ? internal pull-up resistor. rclkx i/o receive clock (serial ports 0, 1). each rclk pin has a 50 k ? internal pull-up resistor. table 2. pin descriptions (continued) pin type function a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open-drai n, t = three-state (when sbts is asserted, or when the adsp-21061 is a bus slave)
adsp-21061 / adsp-21061l rev. d | page 11 of 52 | may 2013 tfsx i/o transmit frame sync (serial ports 0, 1). rfsx i/o receive frame sync (serial ports 0, 1). eboot i eprom boot select. when eboot is high, the adsp-21061 is co nfigured for booting fr om an 8-bit eprom. when eboot is low, the lboot and bms inputs determine booting mode. see the table in the bms pin description below. this signal is a system co nfiguration selection that should be hardwired. lboot i link boot. must be tied to gnd. bms i/o/t* boot memory select. output : used as chip select for boot eprom devices (when eboot = 1, lboot = 0). in a multiprocessor system, bms is output by the bus master. input: when low, indicates that no booting will occur and that adsp-21061 will begin executi ng instructions from external memory. see table below. this input is a system configuration selection that should be hardwired. *three-statable only in eprom boot mode (when bms is an output). eboot lboot bms booting mode 1 0 output eprom (connect bms to eprom chip select.) 0 0 1(input) host processor. 0 0 0 (input) no booting. processor executes from external memory. clkin i clock in. external clock input to the adsp-21061. the inst ruction cycle rate is equal to clkin. clkin may not be halted, changed, or operated below the minimum specified frequency. reset i/a processor reset. resets the adsp-21061 to a known state and begins program execution at the program memory location specified by the ha rdware reset vector address. this input must be asserted (low) at power-up. tck i test clock (jtag). provides an asynchronous clock for jtag boundary scan. tms i/s test mode select (jtag). used to control the test state machine. tms has a 20 k ? internal pull-up resistor. tdi i/s test data input (jtag). provides serial data for the boundary scan logic. tdi has a 20 k ? internal pull-up resistor. tdo o test data output (jtag). serial scan output of the boundary scan path. trst i/a test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the adsp-21061. trst has a 20 k ? internal pull-up resistor. emu o emulation status. must be connected to the adsp-21061 ez-ice target board connector only. emu has a 50 k ? internal pull-up resistor. icsa o reserved. leave unconnected. vdd p power supply . (30 pins). see operating conditions (5 v) and operating conditions (3.3 v) . gnd g power supply return. (30 pins) nc do not connect. reserved pins which must be left open and unconnected. table 2. pin descriptions (continued) pin type function a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open-drai n, t = three-state (when sbts is asserted, or when the adsp-21061 is a bus slave)
rev. d | page 12 of 52 | may 2013 adsp-21061 / adsp-21061l target board connector for ez-ice probe the adsp-2106x ez-ice emulator uses the ieee 1149.1 jtag test access port of the adsp-2106x to monitor and control the target board processor during emulation. the ez-ice probe requires the adsp-2106xs clkin, tms, tck, tdi, tdo, and gnd signals be made accessible on the target system via a 14-pin connector (a 2-row, 7-pin strip header) such as that shown in figure 5 . the ez-ice probe plugs directly onto this connector for chip-on-board emulation. you must add this con- nector to your target board de sign if you intend to use the adsp-2106x ez-ice. the total tr ace length between the ez- ice connector and the farthest de vice sharing the ez-ice jtag pin should be limited to 15 inches maximum for guaranteed operation. this length restriction must include ez-ice jtag signals that are routed to one or more adsp-2106x devices, or a combination of adsp-2106x devi ces and other jtag devices on the chain. the 14-pin, 2-row pin strip header is keyed at the pin 3 loca- tionpin 3 must be removed from the header. the pins must be 0.025 inch square and at least 0. 20 inches in length. pin spacing should be 0.1 ? 0.1 inches. pin strip headers are available from vendors such as 3m, mckenzie, and samtec. the btms, btck, btrst , and btdi signals are provid ed so that the test access port can also be used for board-level testing. when the connector is not bein g used for emulation, place jumpers between the bxxx pins and the xxx pins as shown in figure 5 . if you are not going to use the test access port for board testing, tie btrst to gnd and tie or pull up btck to v dd . the trst pin must be asserted (pulsed low) after power- up (through btrst on the connector) or held low for proper operation of the adsp-2106x. none of the bxxx pins (pins 5, 7, 9, and 11) are connected on the ez-ice probe. the jtag signals are terminated on the ez-ice probe as shown in table 3 . figure 6 shows jtag scan path co nnections for systems that contain multiple adsp-2106x processors. connecting clkin to pin 4 of the ez-ice header is optional. the emulator only uses clkin wh en directed to perform oper- ations such as starting, stoppi ng, and single-stepping multiple adsp-2106xs in a synchronous ma nner. if you do not need these operations to occur synchronously on the multiple proces- sors, simply tie pin 4 of th e ez-ice header to ground. if synchronous multiprocessor operations are needed and clkin is connected, clock skew between the multiple adsp-21061 processors and the clkin pin on the ez-ice header must be minimal. if the skew is too large, synchronous operations may be off by one or more cycles between proces- sors. for synchronous multipro cessor operation tck, tms, clkin, and emu should be treated as cr itical signals in terms of skew, and should be laid ou t as short as possible on your board. if tck, tms, and clkin are driving a large number of adsp-21061s (more than eight) in your system, then treat them as a clock tree using multiple drivers to minimize skew. (see figure 7 below and jtag clock tr ee and clock distribu- tion in the high frequency design considerations section of the adsp-2106x sharc users manual .) if synchronous multiprocessor oper ations are not needed (i.e., clkin is not connected), just use appropriate parallel termina- tion on tck and tms. tdi, tdo, emu, and trst are not critical signals in terms of skew. figure 5. target board connector for adsp-2106x ez-ice emulator (jumpers in place) top view 1 3 14 11 12 910 9 7 8 56 3 4 12 emu gnd tm s tck tr s t tdi tdo gnd key (no pin) btm s btck btr s t btdi gnd table 3. core instruction rate/clkin ratio selection signal termination tms driven through 22 ?? resistor (16 ma driver) tck driven at 10 mhz through 22 ?? resistor (16 ma driver) trst 1 1 trst is driven low until the ez-ice probe is turned on by the emulator at software startup. after software startup, is driven high. active low driven through 22 ? resistor (16 ma driver) (pulled up by on-chip 20 k ? resistor) tdi driven by 22 ?? resistor (16 ma driver) tdo one ttl load, split termination (160/220) clkin one ttl load, split termination (160/220) emu active low, 4.7 k ? pull-up resistor, one ttl load (open-drain output from the dsp)
adsp-21061 / adsp-21061l rev. d | page 13 of 52 | may 2013 figure 6. jtag scan path connections for multiple adsp-2106x systems figure 7. jtag clock tree for multiple adsp-2106x systems e m u t r s t t r s t e m u t r s t ad s p-2106x #1 jtag device (optional) ad s p-2106x n tdi ez-ice jtag connector other jtag controller optional t c k t m s emu tm s tck tdo clkin trst t c k t m s t c k t m s tdi tdo tdi tdo tdo tdi s y s tem clkin emu 5k * tdi tdo 5k tdi emu tm s tck tdo trst clkin *open-drain driver or equivalent, i.e, tdi tdo tdi tdo tdi tdo tdi tdo tdi tdo *
rev. d | page 14 of 52 | may 2013 adsp-21061 / adsp-21061l adsp-21061 specifications operating conditions (5 v) electrical characteristics (5 v) k grade parameter description min nom max unit v dd supply voltage 4.75 5.0 5.25 v t case case operating temperature 0 85 ? c v ih 1 1 1 applies to input and bidirectional pins: data 47C0 , addr 31C0 , rd , wr , sw , ack, sbts , irq 2C0, flag3C0, hgb , cs , dmar1 , dmar2 , br 6C1 , id 2C0 , rpba, cpa , tfs0, tfs1, rfs0, rfs1, eboot, bms , tms, tdi, tck, hbr , dr0, dr1, tclk0, tclk1, rclk0, rclk1. high level input voltage @ v dd = max 2.0 v dd + 0.5 v v ih 2 2 2 applies to input pins: clkin, reset , trst . high level input voltage @ v dd = max 2.2 v dd + 0.5 v v il 1, 2 low level input voltage @ v dd = min C0.5 +0.8 v parameter description test conditions min max unit v oh 1, 2 high level output voltage @ v dd = min, i oh = C2.0 ma 4.1 v v ol 1, 2 low level output voltage @ v dd = min, i ol = 4.0 ma 0.4 v i ih 3, 4 high level input current @ v dd = max, v in = v dd max 10 a i il 3 low level input current @ v dd = max, v in = 0 v 10 a i ilp 4 low level input current @ v dd = max, v in = 0 v 150 a i ozh 5, 6, 7, 8 three-state leakage current @ v dd = max, v in = v dd max 10 a i ozl 5 three-state leakage current @ v dd = max, v in = 0 v 10 a i ozhp three-state leakage current @ v dd = max, v in = v dd max 350 a i ozlc 7 three-state leakage current @ v dd = max, v in = 0 v 1.5 ma i ozla 9 three-state leakage current @ v dd = max, v in = 1.5 v 350 a i ozlar 8 three-state leakage current @ v dd = max, v in = 0 v 4.2 ma i ozls 6 three-state leakage current @ v dd = max, v in = 0 v 150 a c in 10, 11 input capacitance f in = 1 mhz, t case = 25c, v in = 2.5 v 4.7 pf 1 applies to output and bidirectional pins: data 47-0 , addr 31-0 , 3-0, ms 3C0 , rd , wr , page, adrclk, sw , ack, flag3-0, timexp, hbg , redy, dmag1 , dmag2 , br 6C1 , cpa, dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, bms , tdo, emu , icsa. 2 see output drive currents on page 44 for typical drive current capabilities. 3 applies to input pins: ack, sbts , irq 2C0 , hbr , cs , dmar1 , dmar2 , id 2C0 , rpba, eboot, lboot, clkin, reset , tck. 4 applies to input pins with internal pull-ups:dr0, dr1, trst , tms, tdi, emu . 5 applies to three-statable pins: data 47C0 , addr 31C0 , ms 3C0 , rd , wr , page, adrclk, sw , ack, flag 3C0 , hbg , redy, dmag1 , dmag2 , bms , br 6C1 , tfsx, rfsx, tdo, emu . (note that ack is pulled up internally with 2 k ? during reset in a mult iprocessor system, when id 2C0 = 001 and another adsp-2106 1 is not requesting bus mastership.) 6 applies to three-statable pins with internal pu ll-ups: dt0, dt1, tclk0, tclk1, rclk0, rclk1. 7 applies to cpa pin. 8 applies to ack pin when pulle d up. (note that ack is pulled up internally with 2 k ? during reset in a mult iprocessor system, when id 2C0 = 001 and another adsp-21061l is not requesting bus mastership). 9 applies to ack pin when keeper latch enabled. 10 applies to all signal pins. 11 guaranteed but not tested.
adsp-21061 / adsp-21061l rev. d | page 15 of 52 | may 2013 internal power dissipation (5 v) these specifications apply to th e internal power portion of v dd only. see the power dissipation section of this data sheet for cal- culation of external supply current and total supply current. for a complete discussion of the co de used to measure power dissi- pation, see the technical note sharc power dissipation measurements. specifications are based on the operating scenarios: to estimate power consumption fo r a specific application, use the following equation where % is the amount of time your pro- gram spends in that state: %peak i ddinpeak + %high i ddinhigh + %low i ddinlow + %idle i ddidle = power consumption operation peak activity (i ddinpeak ) high activity (i ddinhigh ) low activity (i ddinlow ) instruction type multifunction multifunction single function instruction fetch cache internal memory internal memory core memory access 2 per cycle (dm and pm) 1 per cycle (dm) none internal memory dma 1 per cycle 1 per 2 cycles 1 per 2 cycles parameter test conditions max unit i ddinpeak supply current (internal) 1 t ck = 30 ns, v dd = max t ck = 25 ns, v dd = max t ck = 20 ns, v dd = max 595 680 850 ma ma i ddinhigh supply current (internal) 2 t ck = 30 ns, v dd = max t ck = 25 ns, v dd = max t ck = 20 ns, v dd = max 460 540 670 ma ma i ddinlow supply current (internal) 3 t ck = 30 ns, v dd = max t ck = 25 ns, v dd = max t ck = 20 ns, v dd = max 270 320 390 ma ma i ddidle supply current (idle) 4 i ddidle supply current (idle16) 5 v dd = max v dd = max 200 55 ma ma 1 the test program used to measure i ddinpeak represents worst-case processor operatio n and is not sustainable under normal appl ication conditions. ac tual internal power measurements made using typical appl ications are less than specified. 2 i ddinhigh is a composite average based on a range of high activity code. i ddinlow is a composite avera ge based on a range of low activity code. 3 i ddinlow is a composite average based on a range of low activity code. 4 idle denotes adsp-21061l state duri ng execution of idle instruction. 5 idle16 denotes adsp-2106x state during execution of id le16 instruction.
rev. d | page 16 of 52 | may 2013 adsp-21061 / adsp-21061l external power dissipation (5 v) total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruc- tion execution sequence and the data operands involved. internal power dissipation is ca lculated in the following way: p int = i ddin ?? v dd the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: the number of output pins th at switch during each cycle (o) the maximum frequency at which they can switch (f) their load capacitance (c) their voltage swing (v dd ) and is calculated by: pext = o ? c ? v dd 2 ? f the load capacitance should in clude the processors package capacitance (cin). the switching frequency includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1/(2t ck ). the write strobe can switch every cy cle at a frequency of 1/t ck . select pins switch at 1/(2t ck ), but selects can switch on each cycle. example: estimate p ext with the following assumptions: ? a system with one bank of external data memory ram (32-bit) ? four 128k ? 8 ram chips are used, each with a load of 10 pf ? external data memory writes occur every other cycle, a rate of 1/(4t ck ), with 50% of the pins switching ? the instruction cycl e rate is 40 mhz (t ck = 25 ns) the p ext equation is calculated for each class of pins that can drive: a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: p total = p ext + (i ddin2 ? 5.0 v) note that the conditions causing a worst-case p ext are different from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pi ns are switching from all ones to all zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. table 4. external power calculations pin type no. of pins % switching ? c ? f ? v dd 2 = p ext address 15 50 ? 44.7 pf ? 10 mhz ? 25 v = 0.084 w ms0 10 ? 44.7 pf ? 10 mhz ? 25 v = 0.000 w wr 1 ? 44.7 pf ? 20 mhz ? 25 v = 0.022 w data 32 50 ? 14.7 pf ? 10 mhz ? 25 v = 0.059 w addrclk 1 ? 4.7 pf ? 20 mhz ? 25 v = 0.002 w p ext = 0.167 w
adsp-21061 / adsp-21061l rev. d | page 17 of 52 | may 2013 adsp-21061l specifications operating conditions (3.3 v) electrical characteristics (3.3 v) a grade k grade parameter description min nom max min nom max unit v dd supply voltage 3.15 3.3 3.45 3.15 3.3 3.45 v t case case operating temperature C40 +85 0 +85 ? c v ih 1 1 1 applies to input and bid irectional pins: data 47C0 , addr 31C0 , rd , wr , sw , ack, sbts , irq 2C0, flag3C0, hgb , cs , dmar1 , dmar2 , br 6C1 , id 2C0 , rpba, cpa , tfs0, tfs1, rfs0, rfs1, eboot, bms , tms, tdi, tck, hbr , dr0, dr1, tclk0, tclk1, rclk0, rclk1 high level input voltage @ v dd = max 2.0 v dd + 0.5 2.0 v dd + 0.5 v v ih 2 2 2 applies to input pins: clkin, reset , trst high level input voltage @ v dd = max 2.2 v dd + 0.5 2.2 v dd + 0.5 v v il 1, 2 low level input voltage @ v dd = min C0.5 +0.8 C0.5 +0.8 v parameter description test conditions min max unit v oh 1,2 high level output voltage @ v dd = min, i oh = C2.0 ma 2.4 v v ol 1, 2 low level output voltage @ v dd = min, i ol = 4.0 ma 0.4 v i ih 3, 4 high level input current @ v dd = max, v in = v dd max 10 a i il 3 low level input current @ v dd = max, v in = 0 v 10 a i ilp 4 low level input current @ v dd = max, v in = 0 v 150 a i ozh 5, 6, 7, 8 three-state leakage current @ v dd = max, v in = v dd max 10 a i ozl 5 three-state leakage current @ v dd = max, v in = 0 v 10 a i ozhp three-state leakage current @ v dd = max, v in = v dd max 350 a i ozlc 7 three-state leakage current @ v dd = max, v in = 0 v 1.5 ma i ozla 9 three-state leakage current @ v dd = max, v in = 1.5 v 350 a i ozlar 8 three-state leakage current @ v dd = max, v in = 0 v 4.2 ma i ozls 6 three-state leakage current @ v dd = max, v in = 0 v 150 a c in 10, 11 input capacitance f in = 1 mhz, t case = 25c, v in = 2.5 v 4.7 pf 1 applies to output and bidirectional pins: data 47C0 , addr 31C0 , 3-0, ms 3C0 , rd , wr , page, adrclk, sw , ack, flag3-0, timexp, hbg , redy, dmag1 , dmag2 , br 6C1 , cpa, dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, bms , tdo, emu , icsa. 2 see output drive currents on page 45 for typical drive current capabilities. 3 applies to input pins: ack, sbts , irq 2C0 , hbr , cs , dmar1 , dmar2 , id 2C0 , rpba, eboot, lboot, clkin, reset , tck. 4 applies to input pins with internal pull-ups: dr0, dr1, trst , tms, tdi, emu . 5 applies to three-statable pins: data 47C0 , addr 31C0 , ms 3C0 , rd , wr , page, adrclk, sw , ack, flag 3C0 , hbg , redy, dmag1 , dmag2 , bms , br 6C1 , tfsx, rfsx, tdo, emu . (note that ack is pulled up internally with 2 k ? during reset in a mult iprocessor system, when id 2C0 = 001 and another adsp-2106 1 is not requesting bus mastership.) 6 applies to three-statable pins with internal pu ll-ups: dt0, dt1, tclk0, tclk1, rclk0, rclk1. 7 applies to cpa pin. 8 applies to ack pin when pulle d up. (note that ack is pulled up internally with 2 k ? during reset in a mult iprocessor system, when id 2C0 = 001 and another adsp-21061l is not requesting bus mastership). 9 applies to ack pin when keeper latch enabled. 10 applies to all signal pins. 11 guaranteed but not tested.
rev. d | page 18 of 52 | may 2013 adsp-21061 / adsp-21061l internal power dissipation (3.3 v) these specifications apply to th e internal power portion of v dd only. see the power dissipation section of this data sheet for cal- culation of external supply current and total supply current. for a complete discussion of the co de used to measure power dissi- pation, see the technical note sharc power dissipation measurements. specifications are based on the operating scenarios: to estimate power consumption fo r a specific application, use the following equation where % is the amount of time your pro- gram spends in that state: %peak i ddinpeak + %high i ddinhigh + %low i ddinlow + %idle i ddidle = power consumption operation peak activity (i ddinpeak ) high activity (i ddinhigh ) low activity (i ddinlow ) instruction type multifunction multifunction single function instruction fetch cache internal memory internal memory core memory access 2 per cycle (dm and pm) 1 per cycle (dm) none internal memory dma 1 per cycle 1 per 2 cycles 1 per 2 cycles parameter test conditions max unit i ddinpeak supply current (internal) 1 t ck = 25 ns, v dd = max t ck = 22.5 ns, v dd = max 480 535 ma ma i ddinhigh supply current (internal) 2 t ck = 25 ns, v dd = max t ck = 22.5 ns, v dd = max 380 425 ma ma i ddinlow supply current (internal) 3 t ck = 25 ns, v dd = max t ck = 22.5 ns, v dd = max 220 245 ma ma i ddidle supply current (idle) 4 i ddidle supply current (idle) 5 v dd = max v dd = max 180 50 ma ma 1 the test program used to measure i ddinpeak represents worst-case processor operatio n and is not sustainable under normal appl ication conditions. ac tual internal power measurements made using typical appl ications are less than specified. 2 i ddinhigh is a composite average based on a range of high activity code. i ddinlow is a composite average based on a range of low activity code. 3 iddinlow is a composite average based on a range of low activity code. 4 idle denotes adsp-21061l state duri ng execution of idle instruction. 5 idle16 denotes adsp-21061l state during execution of id le16 instruction.
adsp-21061 / adsp-21061l rev. d | page 19 of 52 | may 2013 external power dissipation (3.3 v) total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruc- tion execution sequence and the data operands involved. internal power dissipation is ca lculated in the following way: p int = i ddin ?? v dd the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: the number of output pins th at switch during each cycle (o) the maximum frequency at which they can switch (f) their load capacitance (c) their voltage swing (v dd ) and is calculated by: pext = o ? c ? v dd 2 ? f the load capacitance should in clude the processors package capacitance (cin). the switching frequency includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1/(2t ck ). the write strobe can switch every cycle at a frequency of 1/t ck . select pins switch at 1/(2t ck ), but selects can switch on each cycle. example: estimate p ext with the following assumptions: ? a system with one bank of external data memory ram (32-bit) ? four 128k ? 8 ram chips are used, each with a load of 10 pf ? external data memory writes occur every other cycle, a rate of 1/(4t ck ), with 50% of the pins switching ? the instruction cycle rate is 40 mhz (t ck = 25 ns) the p ext equation is calculated for each class of pins that can drive: a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: p total = p ext + (i ddin2 ? 3.3 v) note that the conditions causing a worst-case p ext are different from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pi ns are switching from all ones to all zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. table 5. external power calculations pin type no. of pins % switching ? c ? f ? v dd 2 = p ext address 15 50 ? 44.7 pf ? 10 mhz ? 10.9 v = 0.037 w ms0 10 ? 44.7 pf ? 10 mhz ? 10.9 v = 0.000 w wr 1 ? 44.7 pf ? 20 mhz ? 10.9 v = 0.010 w data 32 50 ? 14.7 pf ? 10 mhz ? 10.9 v = 0.026 w addrclk 1 ? 4.7 pf ? 20 mhz ? 10.9 v = 0.001 w p ext = 0.074 w
rev. d | page 20 of 52 | may 2013 adsp-21061 / adsp-21061l absolute maximum ratings stresses greater than those list ed below may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specifica- tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution package marking information the information presented in figure 8 provides details about the package branding for th e adsp-21061 processor. for a complete listing of pr oduct availability, see ordering guide on page 52 . timing specifications the timing specifications sh own are based on a clkin fre- quency of 50 mhz (t ck = 20 ns). the dt derating enables the calculation of timing specifications within the min to max range of the t ck specification (see table 7 ). dt is the difference between the derated clkin period (t ck ) and a clkin period of 25 ns: dt = t ck C 20 ns use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, you cannot meaningfully add parame ters to derive longer times. for voltage reference levels, see figure 29 under test conditions. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. (o/d) = open drain, (a/d) = active drive. switching characteristics specify how the processor changes its signals. you have no control over this timingcircuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell you what the processor will do in a given ci rcumstance. you can also use switching characteristics to ensu re that any timing requirement of a device connected to the processor (such as memory) is satisfied. parameter 5 v 3.3 v supply voltage (v dd ) C0.3 v to +7.0 v C0.3 v to +4.6 v input voltage C0.5 v to v dd +0.5 v C0.5 v to v dd +0.5 v output voltage swing C0.5 v to v dd +0.5 v C0.5 v to v dd +0.5 v load capacitance 200 pf 200 pf storage temperature range C65 ? c to +150 ? cC65 ? c to +150 ? c lead temperature (5 seconds) 280 ? c280 ? c junction temperature under bias 130 ? c130 ? c figure 8. typical package marking (actual marking format may vary) table 6. package brand information brand key field description t temperature range pp package type z lead free option ccc see ordering guide vvvvvv.x assembly lot code n.n silicon revision yyww date code esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality. vvvvvv.x n.n tppzccc s adsp-21061 a yyww country_of_origin
adsp-21061 / adsp-21061l rev. d | page 21 of 52 | may 2013 clock input reset table 7. clock input parameter adsp-21061 50 mhz, 5 v adsp-21061l 44 mhz, 3.3 v adsp-21061/ adsp-21061l 40 mhz, 5 v and 3.3 v adsp-21061 33 mhz, 5 v unit min max min max min max min max timing requirements t ck clkin period 20 100 22.5 100 25 100 30 100 ns t ckl clkin width low 7777ns t ckh clkin width high 5555ns t ckrf clkin rise/fall (0.4 v to 2.0 v) 3 3 3 3 ns figure 9. clock input clkin t ckh t ckl t ck table 8. reset 5 v and 3.3 v unit parameter min max timing requirements t wrst reset pulse width low 1 4t ck ns t srst reset setup before clkin high 2 14 + dt/2 t ck ns 1 applies after the power-up sequence is comp lete. at power-up, the proce ssors internal phase-locked l oop requires no more than 1 00 s while reset is low, assuming stable v dd and clkin (not including startup time of external clock oscillator). 2 only required if multiple adsp-210 61s must come out of reset synchronous to clkin with program counters (pc) equal. not require d for multiple adsp-21061s commu- nicating over the shared bus (through th e external port), because the bus arbitration logic automatically synchronizes itself a fter reset. figure 10. reset clkin reset t wr s t t s r s t
rev. d | page 22 of 52 | may 2013 adsp-21061 / adsp-21061l interrupts timer table 9. interrupts 5 v and 3.3 v unit parameter min max timing requirements t sir irq2C0 setup before clkin high 1 18 + 3dt/4 ns t hir irq2C0 hold before clkin high 1 12 + 3dt/4 ns t ipw irq2C0 pulsewidth 2 2+t ck ns 1 only required for irqx recognition in the following cycle. 2 applies only if t sir and t hir requirements are not met. figure 11. interrupts clkin irq2C0 t ipw t s ir t hir table 10. timer 5 v and 3.3 v unit parameter min max switching characteristic t dtex clkin high to timexp 15 ns figure 12. timer clkin timexp t dtex t dtex
adsp-21061 / adsp-21061l rev. d | page 23 of 52 | may 2013 flags table 11. flags 5 v and 3.3 v unit parameter min max timing requirements t sfi flag3C0 in setup before clkin high 1 8 + 5dt/16 ns t hfi flag3C0 in hold after clkin high 1 0 C 5dt/16 ns t dwrfi flag3C0 in delay after rd /wr low 1 5 + 7dt/16 ns t hfiwr flag3C0 in hold after rd /wr deasserted 1 0ns switching characteristics t dfo flag3C0 out delay after clkin high 16 ns t hfo flag3C0 out hold after clkin high 4 ns t dfoe clkin high to flag3C0 out enable 3 ns t dfod clkin high to flag3C0 out disable 14 ns 1 flag inputs meeting these setup and hold times for instruction cycle n will affect conditional instructions in instruction cycl e n+2. figure 13. flags clkin flag 3 C0 out flag output clkin flag input flag 3 C0 in t dfo t hfo t dfo t dfod t dfoe t s fi t hfi t hfiwr t dwrfi rd wr
rev. d | page 24 of 52 | may 2013 adsp-21061 / adsp-21061l memory readbus master use these specifications for asyn chronous interfacing to memo- ries (and memory-mapped periph erals) without reference to clkin. these specifications apply when the adsp-21061 is the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rd , wr , and dmagx strobe timing parameters only applies to asynchronous access mode. table 12. memory readbus master 5 v and 3.3 v unit parameter min max timing requirements t dad address, selects delay to data valid 1, 2 18 + dt+w ns t drld rd low to data valid 1 12 + 5dt/8 + w ns t hda data hold from address, selects 3 0.5 ns t hdrh data hold from rd high 3 2.0 ns t daak ack delay from address, selects 2, 4 15 + 7dt/8 + w ns t dsak ack delay from rd low 4 8 + dt/2 + w ns switching characteristics t drha address, selects hold after rd high 0+h ns t darl address, selects to rd low 2 2 + 3dt/8 ns t rw rd pulse width 12.5 + 5dt/8 + w ns t rwr rd high to wr , rd , dmagx low 8 + 3dt/8 + hi ns t sadadc address, selects setup before adrclk high 2 0 + dt/4 ns w = (number of wait states specified in wait register) t ck . hi = t ck (if an address hold cycle or bus idle cycle occurs , as specified in wait register; otherwise hi = 0). h = t ck (if an address hold cycle occurs as specified in wait register; otherwise h = 0). 1 data delay/setup: user must meet t dad or t drld or synchronous spec t ssdati . 2 the falling edge of ms x, sw , bms is referenced. 3 data hold: user must meet t hda or t hdrh or synchronous spec t hsdati . see example system hold time calculation on page 43 for the calculation of hol d times given capacitive and dc loads. 4 ack delay/setup: user must meet t daak or t dsak or synchronous specification t sackc ( table 13 on page 25 ) for deassertion of ack (low), all three specificatio ns must be met for assertion of ack (high). figure 14. memory readbus master wr, dmag ack data rd addre ss ms x, sw bms t darl t rw t dad t s adadc t daak t hdrh t hda t rwr t drld addrclk (out) t drha t d s ak
adsp-21061 / adsp-21061l rev. d | page 25 of 52 | may 2013 memory writebus master use these specifications for asyn chronous interfacing to memo- ries (and memory-mapped periph erals) without reference to clkin. these specifications apply when the adsp-21061 is the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rd , wr , and dmagx strobe timing parameters only applies to asynchronous access mode. table 13. memory writebus master 5 v and 3.3 v unit parameter min max timing requirements t daak ack delay from address, selects 1, 2 15 + 7dt/8 + w ns t dsak ack delay from wr low 1 8 + dt/2 + w ns switching characteristics t dawh address, selects to wr deasserted 2 17 + 15dt/16 + w ns t dawl address, selects to wr low 2 3 + 3dt/8 ns t ww wr pulse width 13 + 9dt/16 + w ns t ddwh data setup before wr high 7 + dt/2 + w ns t dwha address hold after wr deasserted 1 + dt/16 + h ns t datrwh data disable after wr deasserted 3 1 + dt/16 + h 6 + dt/16 + h ns t wwr wr high to wr , rd , dmagx low 8 + 7dt/16 + h ns t ddwr data disable before wr or rd low 5 + 3dt/8 + i ns t wde wr low to data enabled C1 + dt/16 ns t sadadc address, selects to adrclk high 2 0 + dt/4 ns w = (number of wait states specified in wait register) t ck . h = t ck (if an address hold cycle occurs, as specified in wait register; otherwise h = 0). i = t ck (if a bus idle cycle occurs, as specified in wait register; otherwise i = 0). 1 ack delay/setup: user must meet t daak or t dsak or synchronous specification t sakc for deassertion of ack (low), all three spec ifications must be met for assertion of ack (high). 2 the falling edge of msx , sw , bms is referenced. 3 for more information, see example system hold time calculation on page 43 for calculation of hold times given capacitive and dc loads. figure 15. memory writebus master rd, dmag ack data wr address msx, sw bms t ww t s adadc t daak t wwr adrclk (out) t dwha t d s ak t dawl t wde t ddwr t datrwh t ddwh t dawh
rev. d | page 26 of 52 | may 2013 adsp-21061 / adsp-21061l synchronous read/writebus master use these specifications for interfacing to external memory sys- tems that require clkinrelative timing or for accessing a slave adsp-21061 (in multipro cessor memory space). these synchronous switching characteri stics are also valid during asynchronous memory reads and writes except where noted (see memory readbus ma ster on page 24 and memory write bus master on page 25 ). when accessing a slave adsp-21061, these switching characteristics must meet the slaves timing requirements for synchronous read/writes (see synchronous read/writebus slave on page 28 ). the slave adsp-21061 must also meet these (bus master ) timing requirements for data and acknowledge setup and hold times. table 14. synchronous read/writebus master 5 v and 3.3 v unit parameter min max timing requirements t ssdati data setup before clkin (50 mhz, t ck = 20 ns) 1 2 + dt/8 1.5 + dt/8 ns t hsdati data hold after clkin 3.5 C dt/8 ns t daak ack delay after address, selects 2, 3 15 + 7dt/8 + w ns t sackc ack setup before clkin 3 6.5+dt/4 ns t hack ack hold after clkin C1 C dt/4 ns switching characteristics t dadro address, msx , bms , sw delay after clkin 2 6.5 C dt/8 ns t hadro address, msx , bms , sw hold after clkin C1 C dt/8 ns t dpgc page delay after clkin 9 + dt/8 16 + dt/8 ns t drdo rd high delay after clkin C1.5 C dt/8 4 C dt/8 ns t dwro wr high delay after clkin (50 mhz, t ck = 20 ns) C2.5 C 3dt/16 C1.5 C 3dt/16 4 C 3dt/16 4 C 3dt/16 ns t drwl rd /wr low delay after clkin 8 + dt/4 12 + dt/4 ns t sddato data delay after clkin 19 + 5dt/16 ns t dattr data disable after clkin 4 0 C dt/8 7 C dt/8 ns t dadcck adrclk delay after clki n 4 + dt/8 10 + dt/8 ns t adrck adrclk period t ck ns t adrckh adrclk width high (t ck /2 C 2) ns t adrckl adrclk width low (t ck /2 C 2) ns 1 this specification applies to the adsp-210 61ks-200 (5 v, 50 mhz) operating at t ck < 25 ns. for all other devices, use the prec eding timing specification of the same name. 2 the falling edge of msx , sw , bms is referenced. 3 ack delay/setup: user must meet t daak or t dsak or synchronous specification t sakc for deassertion of ack (low), all three specifications must be met for assertion of ack (high). 4 see example system hold time calculation on page 43 for calculation of hold times given capacitive and dc loads.
adsp-21061 / adsp-21061l rev. d | page 27 of 52 | may 2013 figure 16. synchronous read/writebus master clkin addrclk addre ss , bms , sw , msx ack (in) page rd data (out) wr data (in) write cycle read cycle t drwl t h s dati t ss dati t drdo t dwro t dattr t s ddato t drwl t dadcck t adrck t adrckl t hadro t dpgc t s ackc t hack t dadro t adrckh t daak
rev. d | page 28 of 52 | may 2013 adsp-21061 / adsp-21061l synchronous read/writebus slave use these specifications for ad sp-21061 bus master accesses of a slaves iop registers or inte rnal memory (in multiprocessor memory space). the bus master must meet these (bus slave) timing requirements. table 15. synchronous read/writebus slave 5 v and 3.3 v unit parameter min max timing requirements t sadri address, sw setup before clkin 14 + dt/2 ns t hadri address, sw hold after clkin 5 + dt/2 ns t srwli rd /wr low setup before clkin 1 8.5 + 5dt/16 ns t hrwli rd /wr low hold after clkin 44 mhz/50 mhz 2 C4 C 5dt/16 C3.5 C 5dt/16 8 + 7dt/16 8 + 7dt/16 ns t rwhpi rd /wr pulse high 3 ns t sdatwh data setup before wr high 3 ns t hdatwh data hold after wr high 1 ns switching characteristics t sddato data delay after clkin 19 + 5dt/16 ns t dattr data disable after clkin 3 0 C dt/8 7 C dt/8 ns t dackad ack delay after address, sw 4 8ns t acktr ack disable after clkin 2 C1 C dt/8 6 C dt/8 ns 1 t srwli (min) = 9.5 + 5dt/16 when mult iprocessor memory space wait state (mmsws bit in wait register) is disabled; when mmsws is enabl ed, t srwli (min)= 4 + dt/8. 2 this specification applies to th e adsp-21061lks-176 (3.3 v, 44 mhz) and the ad sp-21061ks-200 (5 v, 50 mhz), operating at t ck < 25 ns. for all other devices, use the preceding timing specific ation of the same name. 3 see example system hold time calculation on page 43 for calculation of hold times given capacitive and dc loads. 4 t dackad is true only if the address and sw inputs have setup times (before clkin) greater than 10 + dt/8 and less than 19 + 3dt/4. if th e address and inputs have setup times greater than 19 + 3dt/4, then ack is valid 14 + dt/4 (max ) after clkin. a slave that sees an address with an m field matc h will respond with ack regardless of the state of mmsws or strobes. a slave will three-state ack every cycle with t acktr .
adsp-21061 / adsp-21061l rev. d | page 29 of 52 | may 2013 figure 17. synchronous read/writebus slave clkin addre ss , sw ack rd data (out) wr write acce ss data (in) read acce ss t s adri t hadri t dackad t acktr t hrwli t s rwli t s ddato t dattr t s rwli t hrwli t hdatwh t s datwh t rwhpi t rwhpi
rev. d | page 30 of 52 | may 2013 adsp-21061 / adsp-21061l multiprocessor bus request and host bus request use these specifications for passi ng of bus mastership between multiprocessing adsp-21061s (brx ) or a host processor, both synchronous and asynchronous (hbr , hbg ). table 16. multiprocessor bus request and host bus request 5 v and 3.3 v unit parameter min max timing requirements t hbgrcsv hbg low to rd /wr /cs valid 1 20 + 5dt/4 ns t shbri hbr setup before clkin 2 20 + 3dt/4 ns t hhbri hbr hold after clkin 2 14 + 3dt/4 ns t shbgi hbg setup before clkin 13 + dt/2 ns t hhbgi hbg hold after clkin high 6 + dt/2 ns t sbri brx , cpa setup before clkin 3 13 + dt/2 ns t hbri brx , cpa hold after clkin high 6 + dt/2 ns t srpbai rpba setup before clkin 20 + 3dt/4 ns t hrpbai rpba hold after clkin 12 + 3dt/4 ns switching characteristics t dhbgo hbg delay after clkin 7 C dt/8 ns t hhbgo hbg hold after clkin C2 C dt/8 ns t dbro brx delay after clkin 5.5 C dt/8 ns t hbro brx hold after clkin C2 C dt/8 ns t dcpao cpa low delay after clkin 4 6.5 C dt/8 ns t trcpa cpa disable after clkin C2 C dt/8 4.5 C dt/8 ns t drdycs redy (o/d) or (a/d) low from cs and hbr low 5, 6 8ns t trdyhg redy (o/d) disable or redy (a/d) high from hbg 5, 7 44 + 27dt/16 ns t ardytr redy (a/d) disable from cs or hbr high 5 10 ns 1 for first asynchronous access after hbr and cs asserted, addr31-0 must be a non-mms value 1/2 t ck before rd or wr goes low or by t hbgrcsv after hbg goes low. this is easily accomplished by driving an upper address signal high when hbg is asserted. see the host processor control of the adsp-21061 section in the adsp-2106x sharc users manual . 2 only required for recognition in the current cycle. 3 cpa assertion must meet the setup to clkin; deassert ion does not need to meet the setup to clkin. 4 for the adsp-21061l (3.3 v), this specification is 8.5 C dt/8 ns max. 5 (o/d) = open drain, (a/d) = active drive. 6 for the adsp-21061l (3 .3 v), this specific ation is 12 ns max. 7 for the adsp-21061l (3.3 v), this specification is 40 + 23dt/16 ns min.
adsp-21061 / adsp-21061l rev. d | page 31 of 52 | may 2013 figure 18. multiprocessor bus request and host bus request b rx , cpa ( in, o/ d) hbr cs rpba re dy (o/d) redy (a/d) hbg (out) rd wr cs o/d = open-drain, a/ d = active dri ve t s rpbai hb g (i n) clkin hbr hbg (out) brx (out) cp a (out, o/d) t hhbgo t hbro t trcpa t hrpbai t hbri t s bri t s hbgi t hhbgi t dcpao t dbro t dhbgo t hhbri t s hbri t drdyc s t trdyhg t hbgrc s v t ardytr
rev. d | page 32 of 52 | may 2013 adsp-21061 / adsp-21061l asynchronous read/writehost to adsp-21061 use these specifications for asynchronous host processor accesses of an adsp-21061, afte r the host has asserted cs and hbr (low). after hbg is returned by the adsp-21061, the host can drive the rd and wr pins to access the adsp-21061s internal memory or iop registers. hbr and hbg are assumed low for this timing. table 17. read cycle 5 v and 3.3 v unit parameter min max timing requirements t sadrdl address setup/cs low before rd low 1 0ns t hadrdh address hold/cs hold low after rd 0ns t wrwh rd /wr high width 6 ns t drdhrdy rd high delay after redy (o/d) disable 0 ns t drdhrdy rd high delay after redy (a/d) disable 0 ns switching characteristics t sdatrdy data valid before redy disable from low 2 ns t drdyrdl redy (o/d) or (a/d) low delay after rd low 2 10 ns t rdyprd redy (o/d) or (a/d) low pulsewidth for read 45 + dt ns t hdarwh data disable after rd high 2 8 ns 1 not required if rd and address are valid t hbgrcsv after hbg goes low. for first access after hbr asserted, addr31-0 must be a non-mms value 1/2 t clk before rd or wr goes low or by t hbgrcsv after hbg goes low. this is easily acc omplished by driving an upper address signal high when hbg is asserted. see the host processor control of the adsp-21061 section in the adsp-2106x sharc users manual . 2 for the adsp-21061l (3.3 v), this specificat ion is 13.5 ns max. table 18. write cycle 5 v and 3.3 v unit parameter min max timing requirements t scswrl cs low setup before wr low 0 ns t hcswrh cs low hold after wr high 0 ns t sadwrh address setup before wr high 5 ns t hadwrh address hold after wr high 2 ns t wwrl wr low width 8 ns t wrwh rd /wr high width 6 ns t dwrhrdy wr high delay after redy (o/d) or (a/d) disable 0 ns t sdatwh data setup before wr high 50 mhz, t ck = 20 ns 1 3 2.5 ns t hdatwh data hold after wr high 1 ns switching characteristics t drdywrl redy (o/d) or (a/d) low delay after wr /cs low 2 11 ns t rdypwr redy (o/d) or (a/d) low pulsewidth for write 15 ns t srdyck redy (o/d) or (a/d) disable to clkin 1 + 7dt/16 8 + 7dt/16 ns 1 this specification applies to the adsp-210 61ks-200 (5 v, 50 mhz) operating at t ck < 25 ns. for all other devices, use the prec eding timing specification of the same name. 2 for the adsp-21061l (3.3 v), this specificat ion is 13.5 ns max.
adsp-21061 / adsp-21061l rev. d | page 33 of 52 | may 2013 figure 19. synchronous redy timing figure 20. asynchronous read/writehost to adsp-21061 cl k in redy (o/d) o/d = open-drain, a/d = active drive t s rdyck redy (a/d) t s adrdl redy (o/d) rd t drdyrdl t wrwh t hadrdh t hdarwh t r d ypr d t drdhrdy t s dat r d y read cycle addre ss / cs data (out) redy (a/d) o/d = open-drain, a/d = act ive drive t s datwh t hdatwh t ww rl re dy ( o/d ) wr t drdywrl t wrwh t hadwrh t rdypwr t dwrhrdy write cycle t s adwrh da t a ( in ) addre ss redy (a/d) t s c s wrl cs t hc s wrh
rev. d | page 34 of 52 | may 2013 adsp-21061 / adsp-21061l three-state timingbus master, bus slave, hbr , sbts these specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to clkin and the sbts pin. this timing is applicable to bus master transi- tion cycles (btc) and host transi tion cycles (htc) as well as the sbts pin. table 19. three-state timing bus master, bus slave 5 v and 3.3 v unit parameter min max timing requirements t stsck sbts setup before clkin 12 + dt/2 ns t htsck sbts hold before clkin 6 + dt/2 ns switching characteristics t miena address/select enable after clkin C1 C dt/8 ns t miens strobes enable after clkin 1 C1.5 C dt/8 ns t mienhg hbg enable after clkin C1.5 C dt/8 ns t mitra address/select disable after clkin 0 C dt/4 ns t mitrs strobes disable after clkin 1 1.5 C dt/4 ns t mitrhg hbg disable after clkin 2.0 C dt/4 ns t daten data enable after clkin 2 9 + 5dt/16 ns t dattr data disable after clkin 2 0 C dt/8 7 C dt/8 ns t acken ack enable after clkin 2 7.5 + dt/4 ns t acktr ack disable after clkin 2 C1 C dt/8 6 C dt/8 ns t adcen adrclk enable after clkin C2 C dt/8 ns t adctr adrclk disable after clkin 8 C dt/4 ns t mtrhbg memory interface disable before hbg low 3 0 + dt/8 ns t menhbg memory interface enable after hbg high 3 19 + dt ns 1 strobes = rd , wr , page, dmagx , msx , bms , sw . 2 in addition to bus master transition cycles, these specs al so apply to bus master and bus slave synchronous read/write. 3 memory interface = address, rd , wr , msx , sw , page, dmagx , and bms (in eprom boot mode). figure 21. three-state timing (bus transition cycle, sbts assertion) clkin sbts ack clkout data memory interface t mitra, t mitr s , t mitrhg t s t s ck t ht s ck t dattr t daten t acktr t acken t adctr t adcen t miena, t mien s , t mienhg
adsp-21061 / adsp-21061l rev. d | page 35 of 52 | may 2013 figure 22. three-state timing (bus transition cycle, sbts assertion) memory interface hbg memory interface = addre ss , rd , wr , msx , sw ,page, dmagx . bms (in eprom boot mode) t menhbg t mtrhbg
rev. d | page 36 of 52 | may 2013 adsp-21061 / adsp-21061l dma handshake these specifications describe the three dma handshake modes. in all three modes, dmarx is used to initiate transfers. for handshake mode, dmagx controls the latchi ng or enabling of data externally. for external ha ndshake mode, the data transfer is controlled by the addr31C0, rd , wr , sw , page, ms3C0 , ack, and dmag x signals. for paced master mode, the data transfer is controlled by addr31C0, rd , wr , ms3C0 , and ack (not dmag ). for paced master mo de, the memory read- bus master, memory write-bus master, and synchronous read/write-bus master timing specificat ions for addr31C0, rd , wr , ms3C0 , sw , page, data47C0, and ack also apply. table 20. dma handshake 5 v and 3.3 v unit parameter min max timing requirements t sdrlc dmarx low setup before clkin 1 5ns t sdrhc dmarx high setup before clkin 1 5ns t wdr dmarx width low (nonsynchronous) 6 ns t sdatdgl data setup after dmagx low 2 10 + 5dt/8 ns t hdatidg data hold after dmagx high 2 ns t datdrh data valid after dmarx high 2 16 + 7dt/8 ns t dmarll dmarx low edge to low edge 3 23 + 7dt/8 ns t dmarh dmarx width high 6 ns switching characteristics t ddgl dmagx low delay after clkin 9 + dt/4 15 + dt/4 ns t wdgh dmagx high width 6 + 3dt/8 ns t wdgl dmagx low width 12 + 5dt/8 ns t hdgc dmagx high delay after clkin C2 C dt/8 6 C dt/8 ns t vdatdgh data valid before dmagx high 4 8 + 9dt/16 ns t datrdgh data disable after dmagx high 5 07ns t dgwrl wr low before dmagx low 0 2 ns t dgwrh dmag x low before wr high 10 + 5dt/8 +w ns t dgwrr wr high before dmagx high 1 + dt/16 3 + dt/16 ns t dgrdl rd low before dmagx low 0 2 ns t drdgh rd low before dmagx high 11 + 9dt/16 + w ns t dgrdr rd high before dmagx high 0 3 ns t dgwr dmagx high to wr , rd , dmagx low 5 + 3dt/8 + hi ns t dadgh address/select valid to dmagx high 17 + dt ns t ddgha address/select hold after dmagx high 6 C0.5 ns w = (number of wait states specified in wait register) t ck . hi = t ck (if data bus idle cycle occurs, as specified in wait register; otherwise hi = 0). 1 only required for recognition in the current cycle. 2 t sdatdgl is the data setup requirement if dmarx is not being used to hold off compl etion of a write. otherwise, if dmarx low holds off completion of the write, the data can be driven t datdrh after dmarx is brought high. 3 for the adsp-21061l (3.3 v), this specification is 23.5 + 7dt/8 ns min. 4 t vdatdgh is valid if dmarx is not being used to hold off completion of a read. if dmarx is used to prolong the read, then t vdatdgh =t ck C .25t cclk C8+(nt ck ) where n equals the number of extra cycles th at the access is prolonged. 5 see example system hold time calculation on page 43 for calculation of hold times given capacitive and dc loads. 6 for the adsp-21061l (3.3 v), this specificat ion is C1.0 ns min.
adsp-21061 / adsp-21061l rev. d | page 37 of 52 | may 2013 figure 23. dma handshake clkin t s drlc dmarx data data rd wr t wdr t s drhc t dmarh t dmarll t hdgc t wdgh t ddgl dmagx t vdatdgh t datdrh t datrdgh t hdatidg t dgwrl t dgwrh t dgwrr t dgrdl t drdgh t dgrdr t s datdgl *memory read bu s ma s ter, memory write bu s ma s ter, or s ynchronou s read/write bu s ma s ter timing s pecification s for addr 3 1C0, rd , wr , sw ms3C0 ,andackal s o apply here. (external device to external memory) (external memory to external device) tran s fer s between ad s p-2106x internal memory and external device tran s fer s between external device and external memory* (external hand s hake mode) t ddgha addr ms x, sw t dadgh t wdgl (from external device to ad s p-2106x) (from ad s p-2106x to external device)
rev. d | page 38 of 52 | may 2013 adsp-21061 / adsp-21061l serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width. table 21. serial portsexternal clock parameter 5 v and 3.3 v unit min max timing requirements t sfse tfs/rfs setup before tclk/rclk 1 3.5 ns t hfse tfs/rfs hold after tclk/rclk 1, 2 4ns t sdre receive data setup before rclk 1 1.5 ns t hdre receive data hold after rclk 1 4ns t sclkw tclk/rclk width 9 ns t sclk tclk/rclk period t ck ns 1 referenced to sample edge. 2 rfs hold after rck when mce = 1, mfd = 0 is 0 ns minimum from drive edge. tfs hold after tck fo r late external tfs is 0 ns mini mum from drive edge. table 22. serial portsinternal clock parameter 5 v and 3.3 v unit min max timing requirements t sfsi tfs setup before tclk 1 ; rfs setup before rclk 1 8ns t hfsi tfs/rfs hold after tclk/rclk 1, 2 1ns t sdri receive data setup before rclk 1 3ns t hdri receive data hold after rclk 1 3ns 1 referenced to sample edge. 2 rfs hold after rck when mce = 1, mfd = 0 is 0 ns minimum from drive edge. tfs hold after tck fo r late external tfs is 0 ns mini mum from drive edge. table 23. serial portsexternal or internal clock parameter 5 v and 3.3 v unit min max switching characteristics t dfse rfs delay after rclk (internally generated rfs) 1 13 ns t hofse rfs hold after rclk (internally generated rfs) 1 3ns 1 referenced to drive edge. table 24. serial portsexternal clock parameter 5 v and 3.3 v unit min max switching characteristics t dfse tfs delay after tclk (internally generated tfs) 1 13 ns t hofse tfs hold after tclk (internally generated tfs) 1 3ns t ddte transmit data delay after tclk 1 16 ns t hodte transmit data hold after tclk 1 5ns 1 referenced to drive edge.
adsp-21061 / adsp-21061l rev. d | page 39 of 52 | may 2013 table 25. serial portsinternal clock parameter 5 v and 3.3 v unit min max switching characteristics t dfsi tfs delay after tclk (internally generated tfs) 1 4.5 ns t hofsi tfs hold after tclk (internally generated tfs) 1 C1.5 ns t ddti transmit data delay after tclk 1 7.5 ns t hdti transmit data hold after tclk 1 0ns t sclkiw tclk/rclk width t sclk /2 C1.5 t sclk /2+1.5 ns 1 referenced to drive edge. table 26. serial portsenable and three-state parameter 5 v and 3.3 v unit min max switching characteristics t ddten data enable from external tclk 1, 2 4.5 ns t ddtte data disable from external tclk 1 10.5 ns t ddtin data enable from internal tclk 1 0ns t ddtti data disable from internal tclk 1 3ns t dclk tclk/rclk delay from clkin 22 + 3dt/8 ns t dptr sport disable after clkin 17 ns 1 referenced to drive edge. 2 for the adsp-21061l (3 .3 v), this specific ation is 3.5 ns min. table 27. serial portsexternal late frame sync parameter 5 v and 3.3 v unit min max switching characteristics t ddtlfse data delay from late external tfs or external rfs with mce = 1, mfd = 0 1 12 ns t ddtenfs data enable from late fs or mce = 1, mfd = 0 1 3.5 ns 1 mce = 1, tfs enable and tfs valid follow t ddtlfse and t ddtenfs .
rev. d | page 40 of 52 | may 2013 adsp-21061 / adsp-21061l figure 24. serial ports dt dt drive edge drive edge drive edge drive edge tclk/rclk tclk (int) tclk/rclk tclk (ext) rclk rf s dr drive edge s ample edge data receive internal clock data receive external clock rclk rf s dr drive edge s ample edge note: either the ri s ing edge or falling edge of rclk, tclk can be u s ed a s the active s ampling edge. tclk tf s dt drive edge s ample edge tclk tf s dt drive edge s ample edge data tran s mit internal clock data tran s mit external clock note: either the ri s ing edge or falling edge of rclk, tclk can be u s ed a s the active s ampling edge. t ddtte t ddten t ddtti t ddtin t s dri t hdri t s f s i t hf s i t df s e t hof s e t s clkiw t s dre t hdre t s f s e t hf s e t df s e t s clkw t hof s e t ddti t hdti t s f s i t hf s i t s clkiw t df s i t hof s i t ddte t hdte t s f s e t hf s e t df s e t s clkw t hof s e clkin t dptr s port di s able delay from in s truction tclk, rclk tf s ,rf s ,dt tclk (int) rclk (int) s port enable and three- s tate latency i s two cycle s t dclk low to high only t s tf s ck clkin t htf s ck note: applie s only to gated s erial clock mode with external tf s ,a s u s ed in the s erial port s y s tem i/o for me s hmultiproce ss ing. tf s (ext)
adsp-21061 / adsp-21061l rev. d | page 41 of 52 | may 2013 figure 25. serial portsexternal late frame sync drive sample drive tclk tfs dt drive sample drive late external tfs external rfs with mce = 1, mfd = 0 1st bit 2nd bit dt rclk rfs 1st bit 2nd bit t hofse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i t hofse/i t sfse/i t ddte/i t ddtlfse t hdte/i t ddtenfs
rev. d | page 42 of 52 | may 2013 adsp-21061 / adsp-21061l jtag test access port and emulation for jtag test access port and emulation, see table 28 and figure 26 . table 28. jtag test access port and emulation parameter 5 v and 3.3 v unit min max timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high t ck ns t htap tdi, tms hold after tck high 6 ns t ssys system inputs setup before tck low 1 7ns t hsys system inputs hold after tck low 1 18 ns t trstw trst pulse width 4t ck ns switching characteristics t dtdo tdo delay from tck low 13 ns t dsys system outputs delay after tck low 2 18.5 ns 1 system inputs = da ta47C0, addr31C0, rd , wr , ack, sbts , hbr , hbg , cs , dmar1 , dmar2 , br6C1 , id2C0, rpba, irq2C0 , flag3C0, cpa , dr0, dr1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, eboot, lboot, bms , clkin, reset . 2 system outputs = data47C0, addr31C0, ms3C0 , rd , wr , sw , ack, adrclk, clkout, hbg , redy, dmag1 , dmag2 , br6C1 , cpa , flag3C0, timexp, dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, bms . figure 26. jtag test ac cess port and emulation tck tm s tdi tdo s y s tem input s s y s tem output s t s tap t tck t htap t dtdo t ss y s t h s y s t d s y s
adsp-21061 / adsp-21061l rev. d | page 43 of 52 | may 2013 test conditions output disable time output pins are considered to be disabled when they stop driv- ing, go into a high impedance stat e, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ? v is dependent on the capacitive load, c l , and the load current, i l . this decay time can be approximated by the following equation: the output disable time t dis is the difference between t measured and t decay as shown in figure 27 . the time t measured is the interval from when the refere nce signal switches to when the output voltage decays ? v from the measured output high or output low voltage. t decay is calculated with test loads c l and i l , and with ? v equal to 0.5 v. output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driv- ing. the output enable time t ena is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram ( figure 27 ). if multiple pins (such as the data bus) ar e enabled, the measurement value is that of the first pin to start driving. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose ? v to be the difference between the adsp-21061s output voltage and the input threshold for the de vice requiring the hold time. a typical ? v will be 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or th ree-state current (per data line). the hold time will be t decay plus the minimum disable time (i.e., t datrwh for the write cycle). output drive characteristics figure 30 through figure 37 show typical char acteristics for the output drivers of the adsp-21061 (5 v) and adsp-21061l (3 v). the curves represent the current drive capability and switching behavior of the output drivers as a function of resistive and capacitive loading. capacitive loading output delays and holds are based on standard capacitive loads: 50 pf on all pins (see figure 28 ). the delay and hold specifica- tions given should be derated by a factor of 1.5 ns/50 pf for loads other than the no minal value of 50 pf. figure 31 , figure 32 , figure 35 , and figure 36 show how output rise time varies with capacitance. figure 33 and figure 37 show graphi- cally how output delays and hold s vary with load capacitance. (note that this graph or derating does not apply to output dis- able delays; see the previous se ction output disable time under test conditions.) the graphs of figure 31 , figure 32 , figure 35 , and figure 36 may not be linear outside the ranges shown. figure 27. output enable/disable p ext c l v ? i l -------------- - = reference s ignal t di s output starts driving v oh (mea s ured) - v v ol (mea s ured) + v t mea s ured v oh (mea s ured) v ol (mea s ured) 2.0v 1.0v v oh (mea s ured) v ol (mea s ured) high impedance s tate. te s tcondition s cau s e thi s voltage to be approximately 1.5v. output s top s driving t ena t decay figure 28. euivalent device loading for ac measurements (includes all fixtures) figure 29. voltage reference levels for ac measurements (except output enale/disale) 1.5v 50pf to output pin i ol i oh input or output 1.5v 1.5v
rev. d | page 44 of 52 | may 2013 adsp-21061 / adsp-21061l output characteristics (5 v) figure 30. typical ou tput drive currents (v dd = 5 v) figure 31. typical output rise time (10% to 90% v dd ) vs. load capacitance (v dd = 5 v) s ource voltage (v) - 75 - 150 05.25 s o u r c e c u r r e n t ( m a ) 0.75 1.50 2.25 3 .00 3 .75 4.50 75 - 50 - 100 - 125 25 - 25 50 0 4.75v, +100c 4.75v,+ 100c 5.0v, +25c 5.25v, - 40c 5.0v, +25c 5.25v, - 40c load capacitance (pf) 16.0 8 .0 0 0200 20 40 60 8 0 100 120 140 160 1 8 0 14.0 12.0 4.0 2.0 10.0 6.0 fall tim e ri s etime r i s e a n d f a l l t i m e s ( n s ) ( 0 . 5 v t o 4 . 5 v , 1 0 % t o 9 0 % ) y = 0.005x + 3 .7 y = 0.00 3 1x + 1.1 figure 32. typical output rise time (0.8 v to 2.0 v) vs. load capacitance (v dd = 5 v) figure 33. typical output delay or hold vs. load capacitance (at maximum case temperature) (v dd = 5 v) 3 .5 0 r i s e a n d f a l l t i m e s ( n s ) ( 0 . 8 v t o 2 . 0 v ) 3 .0 2.5 2.0 1.5 1.0 0.5 load capacitance (pf) 0200 20 40 60 8 0 100 120 140 160 1 8 0 fall tim e ri s etime y = 0.009x + 1.1 y = 0.005x + 0.6 load capacitance (pf) o u t p u t d e l a y o r h o l d ( n s ) 5 - 1 25 200 50 75 100 125 150 175 4 3 2 1 nominal y=0.0 3 x - 1.45
adsp-21061 / adsp-21061l rev. d | page 45 of 52 | may 2013 input/output characteristics (3.3 v) figure 34. typical drive currents (v dd = 3.3 v) figure 35. typical output rise time (10% to 90% v dd ) vs. load capacitance (v dd = 3.3 v) s ource voltage (v) 120 - 20 - 8 0 0 3 .5 s o u r c e c u r r e n t ( m a ) 0.5 1.0 1.5 2.0 2.5 3 .0 100 0 - 40 - 60 60 20 8 0 40 - 100 - 120 3 .0v, + 8 5c 3 . 3 v, + 2 5 c 3 .6v, - 40c 3 .6v, - 40c 3 . 3 v, + 25 c 3 .0v, + 8 5c v oh v ol load capacitance (pf) 0 2 0 20 40 60 8 0100120 y = 0.0796x + 1.17 y = 0.0467x + 0.55 ri s etime fall time 140 160 1 8 0200 4 6 8 10 12 14 16 1 8 s e a n d f a l l t i m e s ( n s ) ( 1 0 % t o 9 0 % ) figure 36. typical output rise time (0.8 v to 2.0 v) vs. load capacitance (v dd = 3.3 v) figure 37. typical output delay or hold vs. load capacitance (at maximum case temperature) (v dd = 3.3 v) load capacitance (pf) 0 0 20 40 60 8 0 100 120 y=0.0 3 91x + 0. 3 6 y=0.0 3 05x + 0.24 ri s etime fall time 140 160 1 8 0200 r i s e a n d f a l l t i m e s ( n s ) ( 0 . 8 v t o 2 . 0 v ) 1 2 3 4 5 6 7 8 9 load capacitance (pf) o u t p u t d e l a y o r h o l d ( n s ) 5 - 1 25 200 50 75 100 125 150 175 4 3 2 1 nominal y=0.0 3 29x - 1.65
rev. d | page 46 of 52 | may 2013 adsp-21061 / adsp-21061l environmental conditions thermal characteristics the adsp-21061 is available in 240-lead thermally enhanced mqfp package. the top surfac e of the therma lly enhanced mqfp contains a metal slug from which most of the die heat is dissipated. the slug is flush with the top surface of the package. note that the metal slug is internally connected to gnd through the device substrate. the adsp-21061l is available in 240-lead mqfp and 225-ball plastic bga packages. all packages are specified for a case temperature (t case ). to ensure that the t case is not exceeded, a heatsink and/or an air- flow source may be used. a heat sink should be attached with a thermal adhesive. t case = t amb + (pd ? ca ) t case = case temperature (measure d on top surface of package) t amb = ambient temperature ? c pd =power dissipation in w (t his value depends upon the spe- cific application; a method for calculating pd is shown under power dissipation). ? ca =value from tables below. table 29. adsp-21061 (5 v th ermally enhanced ed/mqfp package) parameter condition (linear ft./min.) typical unit ? ca airflow = 0 airflow = 100 airflow = 200 airflow = 400 airflow = 600 10 9 8 7 6 c/w table 30. adsp-21061l (3.3 v mqfp package) parameter condition (linear ft./min.) typical unit ? ca airflow = 0 airflow = 100 airflow = 200 airflow = 400 airflow = 600 19.6 17.6 15.6 13.9 12.2 c/w table 31. adsp-21061l (3.3 v pbga package) parameter condition (linear ft./min.) typical unit ? ca airflow = 0 airflow = 200 airflow = 400 19.0 13.6 11.2 c/w
adsp-21061 / adsp-21061l rev. d | page 47 of 52 | may 2013 225-ball pbga pin configurations table 32. adsp-21061l 225-lead metric pbga (b-225-2) pin assignments pin name pbga pin number pin name pbga pin number pin name pbga pin number pin name pbga pin number pin name pbga pin number bms a01 addr25 d01 addr14 g01 addr6 k01 emu n01 addr30 a02 addr26 d02 addr15 g02 addr5 k02 tdo n02 dmar2 a03 ms2 d03 addr16 g03 addr3 k03 irq0 n03 dt1 a04 addr29 d04 addr19 g04 addr0 k04 irq1 n04 rclk1 a05 dmar1 d05 gnd g05 icsa k05 id2 n05 tclk0 a06 tfs1 d06 v dd g06 gnd k06 nc n06 rclk0 a07 cpa d07 v dd g07 v dd k07 nc n07 adrclk a08 hbg d08 v dd g08 v dd k08 nc n08 cs a09 dmag2 d09 v dd g09 v dd k09 nc n09 clkin a10 br5 d10 v dd g10 gnd k10 nc n10 page a11 br1 d11 gnd g11 gnd k11 nc n11 br3 a12 data40 d12 data22 g12 data8 k12 nc n12 data47 a13 data37 d13 data25 g13 data11 k13 nc n13 data44 a14 data35 d14 data24 g14 data13 k14 data1 n14 data42 a15 data34 d15 data23 g15 data14 k15 data3 n15 ms0 b01 addr21 e01 addr12 h01 addr2 l01 trst p01 sw b02 addr22 e02 addr11 h02 addr1 l02 tms p02 addr31 b03 addr24 e03 addr13 h03 flag0 l03 eboot p03 hbr b04 addr27 e04 addr10 h04 flag3 l04 id0 p04 dr1 b05 gnd e05 gnd h05 rpba l05 nc p05 dt0 b06 gnd e06 v dd h06 gnd l06 nc p06 dr0 b07 gnd e07 v dd h07 gnd l07 nc p07 redy b08 gnd e08 v dd h08 gnd l08 nc p08 rd b09 gnd e09 v dd h09 gnd l09 nc p09 ack b10 gnd e10 v dd h10 gnd l10 nc p10 br6 b11 nc e11 gnd h11 nc l11 nc p11 br2 b12 data33 e12 data18 h12 data4 l12 nc p12 data45 b13 data30 e13 data19 h13 data7 l13 nc p13 data43 b14 data32 e14 data21 h14 data9 l14 nc p14 data39 b15 data31 e15 data20 h15 data10 l15 data0 p15 ms3 c01 addr17 f01 addr9 j01 flag1 m01 tck r01 ms1 c02 addr18 f02 addr8 j02 flag2 m02 irq2 r02 addr28 c03 addr20 f03 addr7 j03 timexp m03 reset r03 sbts c04 addr23 f04 addr4 j04 tdi m04 id1 r04 tclk1 c05 gnd f05 gnd j05 lboot (gnd) m05 nc r05 rfs1 c06 gnd f06 v dd j06 nc m06 nc r06 tfs0 c07 v dd f07 v dd j07 nc m07 nc r07 rfs0 c08 v dd f08 v dd j08 nc m08 nc r08 wr c09 v dd f09 v dd j09 nc m09 nc r09 dmag1 c10 gnd f10 v dd j10 nc m10 nc r10 br4 c11 gnd f11 gnd j11 nc m11 nc r11 data46 c12 data29 f12 data12 j12 nc m12 nc r12
rev. d | page 48 of 52 | may 2013 adsp-21061 / adsp-21061l data41 c13 data26 f13 data15 j13 data2 m13 nc r13 data38 c14 data28 f14 data16 j14 data5 m14 nc r14 data36 c15 data27 f15 data17 j15 data6 m15 nc r15 figure 38. bga pin assignments (top view, summary) table 32. adsp-21061l 225-lead metric pbga (b-225-2) pin assign ments (continued) pin name pbga pin number pin name pbga pin number pin name pbga pin number pin name pbga pin number pin name pbga pin number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r adrclk bms addr30 dmar2 dt1 rclk1 tclk0 rclk0 cs clkin page br3 data47 data44 data42 ms0 sw addr31 hbr dr1 dt0 dr0 redy rd ack br6 br2 data45 data43 data39 ms3 ms1 addr28 sbts tclk1 rfs1 tfs0 rfs0 wr dmag1 br4 data46 data41 data38 data36 addr25 addr26 ms2 addr29 dmar1 tfs1 cpa hbg dmag2 br5 br1 data40 data37 data35 data34 addr21 addr22 addr24 addr27 gnd gnd gnd gnd gnd gnd nc data33 data30 data32 data31 addr17 addr18 addr20 addr23 gnd gnd v d d v dd v dd gnd gnd data29 data26 data28 data27 addr14 addr15 addr16 addr19 gnd v dd v dd v dd v dd v dd gnd data22 data25 data24 data23 addr12 addr11 addr13 addr10 gnd v dd v dd v dd v dd v dd gnd data18 data19 data21 data20 addr9 addr8 addr7 addr4 gnd v dd v dd v dd v dd v dd gnd data12 data15 data16 data17 addr6 addr5 addr3 addr0 icsa gnd v dd v dd v dd gnd gnd data8 data11 data13 data14 addr2 addr1 flag0 flag3 rpba gnd gnd gnd gnd gnd nc data4 data7 data9 data10 flag1 flag2 timexp tdi lboot (gnd) nc nc nc nc nc nc nc data2 data5 data6 emu tdo irq1 id2 nc nc nc nc nc nc nc nc data1 data3 trst tms eboot id0 nc nc nc nc nc nc nc nc nc nc data0 tck irq2 reset id1 nc nc nc nc nc nc nc nc nc nc nc nc = no connect irq0
adsp-21061 / adsp-21061l rev. d | page 49 of 52 | may 2013 240-lead mqfp pin configurations table 33. adsp-21061 mqfp/ed (sp-240); ad sp-21061l mqfp (s-240) pin assignments pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. tdi 1 addr20 41 tclk0 81 data41 121 data14 161 nc 201 trst 2 addr21 42 tfs0 82 data40 122 data13 162 nc 202 v dd 3gnd 43 dr0 83 data39 123 data12 163 nc 203 tdo 4 addr22 44 rclk0 84 v dd 124 gnd 164 nc 204 timexp 5 addr23 45 rfs0 85 data38 125 data11 165 v dd 205 emu 6addr2446v dd 86 data37 126 data10 166 nc 206 icsa 7 v dd 47 v dd 87 data36 127 data9 167 nc 207 flag3 8 gnd 48 gnd 88 gnd 128 v dd 168 nc 208 flag2 9 v dd 49 adrclk 89 nc 129 data8 169 nc 209 flag110addr2550redy90data35130data7170nc 210 flag011addr2651hbg 91 data34 131 data6 171 nc 211 gnd12addr2752cs 92 data33 132 gnd 172 gnd 212 addr0 13 gnd 53 rd 93 v dd 133 data5 173 nc 213 addr1 14 ms3 54 wr 94 v dd 134 data4 174 nc 214 v dd 15 ms2 55 gnd 95 gnd 135 data3 175 nc 215 addr2 16 ms1 56 v dd 96 data32 136 v dd 176 nc 216 addr3 17 ms0 57 gnd 97 data31 137 data2 177 nc 217 addr4 18 sw 58 clkin 98 data30 138 data1 178 nc 218 gnd 19 bms 59 ack 99 gnd 139 data0 179 v dd 219 addr520addr2860dmag2 100 data29 140 gnd 180 gnd 220 addr6 21 gnd 61 dmag1 101 data28 141 gnd 181 v dd 221 addr7 22 v dd 62 page 102 data27 142 nc 182 nc 222 v dd 23 v dd 63 v dd 103 v dd 143 nc 183 nc 223 addr824addr2964br6 104 v dd 144 nc 184 nc 224 addr925addr3065br5 105 data26 145 nc 185 nc 225 addr10 26 addr31 66 br4 106 data25 146 nc 186 nc 226 gnd 27 gnd 67 br3 107 data24 147 nc 187 nc 227 addr11 28 sbts 68 br2 108 gnd 148 v dd 188 gnd 228 addr12 29 dmar2 69 br1 109 data23 149 nc 189 id2 229 addr13 30 dmar1 70 gnd 110 data22 150 nc 190 id1 230 v dd 31 hbr 71 v dd 111 data21 151 nc 191 id0 231 addr14 32 dt1 72 gnd 112 v dd 152 nc 192 lboot (gnd) 232 addr15 33 tclk1 73 data47 113 data20 153 nc 193 rpba 233 gnd 34 tfs1 74 data46 114 data19 154 nc 194 reset 234 addr16 35 dr1 75 data45 115 data18 155 gnd 195 eboot 235 addr17 36 rclk1 76 v dd 116 gnd 156 gnd 196 irq2 236 addr18 37 rfs1 77 data44 117 data17 157 v dd 197 irq1 237 v dd 38 gnd 78 data43 118 data16 158 nc 198 irq0 238 v dd 39 cpa 79 data42 119 data15 159 nc 199 tck 239 addr19 40 dt0 80 gnd 120 v dd 160 nc 200 tms 240
rev. d | page 50 of 52 | may 2013 adsp-21061 / adsp-21061l outline dimensions figure 39. 240-lead metric qu ad flat package, thermally enhanced [mqfp/ed] (sp-240-2) 0.66 0.56 0.46 4.10 3.78 3.55 seating plane view a 0.38 0.25 0.20 0.09 0.076 coplanarity 3.50 3.40 3.30 7 0 view a rotated 90 ccw 1 240 181 180 121 120 61 60 pin 1 heat slug top view (pins down) 34.60 bsc sq 29.50 ref sq 32.00 bsc sq 3.92 45 (4 places) 24.00 ref sq 0.27 max 0.17 min 0.50 bsc lead pitch
adsp-21061 / adsp-21061l rev. d | page 51 of 52 | may 2013 figure 40. 240-lead metric quad flat package, [mqfp] (s-240) figure 41. 225-ball plastic ball grid array [pbga] (b-225-2) 1 1 8 1 0 4 2 180 121 120 61 60 34.85 34.60 sq 34.35 32.00 bsc sq 29.50 ref sq seating plane 4.10 max 0.75 0.60 0.45 0.50 0.25 3. 5 0 3.40 3.20 0.27 0.17 0.50 bsc 0.08 max coplanarity pin 1 2.70 max 1.27 bsc 18.00 bsc sq a b c d e f g h j k l m n p r 15 14 13 12 11 10 9 8 7 6 5 42 31 top view 1.30 1.20 1.10 0.15 max coplanarity 0.70 0.60 0.50 detail a 0.90 0.75 0.60 ball diameter bottom view detail a a1 corner index area 20.10 20.00 sq 19.90 23.20 23.00 sq 22.80 ball a1 indicator 0.50 r 3 places seating plane
rev. d | page 52 of 52 | may 2013 adsp-21061 / adsp-21061l ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00170-0-5/13(d) surface-mount design table 34 is provided as an aide to pcb design. for industry -standard design recommenda tions, refer to ipc-7351, generic requirements for surface-mount design and land pattern standard . ordering guide table 34. bga data for use with surface-mount design package ball attach type solder mask opening ball pad size 225-ball grid array (pbga) solder mask defined 0.63 mm diameter 0.73 mm diameter model notes temperature range instruction rate on-chip sram operating voltage package description package option adsp-21061ks-133 0 ? c to 85 ? c 33 mhz 1m bit 5 v 240-lead mqfp_ed sp-240-2 adsp-21061ksz-133 1 1 z = rohs compliant part. 0 ? c to 85 ? c 33 mhz 1m bit 5 v 240-lead mqfp_ed sp-240-2 adsp-21061ks-160 0 ? c to 85 ? c 40 mhz 1m bit 5 v 240-lead mqfp_ed sp-240-2 adsp-21061ksz-160 1 0 ? c to 85 ? c 40 mhz 1m bit 5 v 240-lead mqfp_ed sp-240-2 adsp-21061ks-200 0 ? c to 85 ? c 50 mhz 1m bit 5 v 240-lead mqfp_ed sp-240-2 adsp-21061ksz-200 1 0 ? c to 85 ? c 50 mhz 1m bit 5 v 240-lead mqfp_ed sp-240-2 ADSP-21061LKB-160 0 ? c to 85 ? c 40 mhz 1m bit 3.3 v 225-ball pbga b-225-2 adsp-21061lkbz-160 1 0 ? c to 85 ? c 40 mhz 1m bit 3.3 v 225-ball pbga b-225-2 adsp-21061lksz-160 1 0 ? c to 85 ? c 40 mhz 1m bit 3.3 v 240-lead mqfp s-240 adsp-21061lasz-176 1 C40 ? c to +85 ? c 44 mhz 1m bit 3.3 v 240-lead mqfp s-240 adsp-21061lksz-176 1 0 ? c to 85 ? c 44 mhz 1m bit 3.3 v 240-lead mqfp s-240

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